Merge pull request #535 from antmicro/arty-cv32e40p
Add support for the CV32E40P RISC-V CPU
This commit is contained in:
enjoy-digital
GitHub
commit
4c4cd335de
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@ -57,6 +57,7 @@ from litex.soc.cores.cpu.minerva import Minerva
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from litex.soc.cores.cpu.vexriscv import VexRiscv
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from litex.soc.cores.cpu.rocket import RocketRV64
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from litex.soc.cores.cpu.blackparrot import BlackParrotRV64
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from litex.soc.cores.cpu.cv32e40p import CV32E40P
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CPUS = {
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# None
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@ -76,6 +77,7 @@ CPUS = {
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"picorv32" : PicoRV32,
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"minerva" : Minerva,
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"vexriscv" : VexRiscv,
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"cv32e40p" : CV32E40P,
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# RISC-V 64-bit
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"rocket" : RocketRV64,
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@ -0,0 +1 @@
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from litex.soc.cores.cpu.cv32e40p.core import CV32E40P
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@ -0,0 +1,4 @@
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.section .text, "ax", @progbits
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.global boot_helper
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boot_helper:
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jr x13
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@ -0,0 +1,417 @@
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#!/usr/bin/env python3
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import os
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import re
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from migen import *
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from migen.fhdl.specials import Tristate
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from litex import get_data_mod
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from litex.soc.interconnect import wishbone, stream
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from litex.soc.interconnect.csr import *
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from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
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CPU_VARIANTS = ["standard", "full"]
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GCC_FLAGS = {
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# /-------- Base ISA
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# |/------- Hardware Multiply + Divide
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# ||/----- Atomics
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# |||/---- Compressed ISA
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# ||||/--- Single-Precision Floating-Point
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# |||||/-- Double-Precision Floating-Point
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# imacfd
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"standard": "-march=rv32imc -mabi=ilp32 ",
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"full": "-march=rv32imfc -mabi=ilp32 ",
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}
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obi_layout = [
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("req", 1),
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("gnt", 1),
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("addr", 32),
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("we", 1),
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("be", 4),
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("wdata", 32),
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("rvalid", 1),
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("rdata", 32),
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]
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apb_layout = [
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("paddr", 32),
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("pwdata", 32),
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("pwrite", 1),
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("psel", 1),
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("penable", 1),
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("prdata", 32),
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("pready", 1),
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("pslverr", 1),
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]
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trace_layout = [
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("ivalid", 1),
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("iexception", 1),
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("interrupt", 1),
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("cause", 5),
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("tval", 32),
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("priv", 3),
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("iaddr", 32),
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("instr", 32),
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("compressed", 1),
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]
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def add_manifest_sources(platform, manifest):
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basedir = get_data_mod("cpu", "cv32e40p").data_location
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with open(os.path.join(basedir, manifest), 'r') as f:
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for l in f:
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res = re.search('\$\{DESIGN_RTL_DIR\}/(.+)', l)
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if res and not re.match('//', l):
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if re.match('\+incdir\+', l):
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platform.add_verilog_include_path(os.path.join(basedir, 'rtl', res.group(1)))
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else:
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platform.add_source(os.path.join(basedir, 'rtl', res.group(1)))
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class OBI2Wishbone(Module):
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def __init__(self, obi, wb):
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dat_r_d = Signal().like(wb.dat_r)
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addr_d = Signal().like(obi.addr)
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ack_d = Signal()
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self.sync += [
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dat_r_d.eq(wb.dat_r),
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ack_d.eq(wb.ack),
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addr_d.eq(obi.addr),
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]
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self.comb += [
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wb.adr.eq(obi.addr[2:32]),
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wb.stb.eq(obi.req & (~ack_d)),
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wb.dat_w.eq(obi.wdata),
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wb.cyc.eq(obi.req),
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wb.sel.eq(obi.be),
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wb.we.eq(obi.we),
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obi.gnt.eq(wb.ack & (addr_d == obi.addr)),
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obi.rvalid.eq(ack_d),
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obi.rdata.eq(dat_r_d),
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]
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class Wishbone2OBI(Module):
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def __init__(self, wb, obi):
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(wb.cyc & wb.stb,
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obi.req.eq(1),
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NextState("ACK"),
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)
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)
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fsm.act("ACK",
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wb.ack.eq(1),
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NextState("IDLE"),
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)
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self.comb += [
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obi.we.eq(wb.we),
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obi.be.eq(wb.sel),
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obi.addr.eq(Cat(0, 0, wb.adr)),
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obi.wdata.eq(wb.dat_w),
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wb.dat_r.eq(obi.rdata),
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]
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class Wishbone2APB(Module):
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def __init__(self, wb, apb):
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(wb.cyc & wb.stb,
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NextState("ACK"),
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)
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)
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fsm.act("ACK",
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apb.penable.eq(1),
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wb.ack.eq(1),
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NextState("IDLE"),
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)
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self.comb += [
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apb.paddr.eq(Cat(0, 0, wb.adr)),
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apb.pwrite.eq(wb.we),
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apb.psel.eq(1),
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apb.pwdata.eq(wb.dat_w),
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wb.dat_r.eq(apb.prdata),
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]
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class TraceCollector(Module, AutoCSR):
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def __init__(self, trace_depth=16384):
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self.bus = bus = wishbone.Interface()
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self.sink = sink = stream.Endpoint([("data", 32)])
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clear = Signal()
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enable = Signal()
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pointer = Signal(32)
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self._enable = CSRStorage()
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self._clear = CSRStorage()
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self._pointer = CSRStatus(32)
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mem = Memory(32, trace_depth)
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rd_port = mem.get_port()
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wr_port = mem.get_port(write_capable=True)
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self.specials += rd_port, wr_port, mem
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self.sync += [
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# wishbone
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bus.ack.eq(0),
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If(bus.cyc & bus.stb & ~bus.ack, bus.ack.eq(1)),
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# trace core
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If(clear, pointer.eq(0)).Else(
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If(sink.ready & sink.valid, pointer.eq(pointer+1)),
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),
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]
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self.comb += [
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# wishbone
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rd_port.adr.eq(bus.adr),
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bus.dat_r.eq(rd_port.dat_r),
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# trace core
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wr_port.adr.eq(pointer),
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wr_port.dat_w.eq(sink.data),
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wr_port.we.eq(sink.ready & sink.valid),
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sink.ready.eq(enable & (pointer < trace_depth)),
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# csrs
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enable.eq(self._enable.storage),
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clear.eq(self._clear.storage),
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self._pointer.status.eq(pointer),
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]
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class TraceDebugger(Module):
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def __init__(self):
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self.bus = wishbone.Interface()
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self.source = source = stream.Endpoint([("data", 32)])
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self.trace_if = trace_if = Record(trace_layout)
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apb = Record(apb_layout)
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self.submodules.bus_conv = Wishbone2APB(self.bus, apb)
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self.trace_params = dict(
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i_clk_i=ClockSignal(),
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i_rst_ni=~ResetSignal(),
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i_test_mode_i=0,
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# cpu interface
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i_ivalid_i=trace_if.ivalid,
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i_iexception_i=trace_if.iexception,
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i_interrupt_i=trace_if.interrupt,
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i_cause_i=trace_if.cause,
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i_tval_i=trace_if.tval,
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i_priv_i=trace_if.priv,
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i_iaddr_i=trace_if.iaddr,
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i_instr_i=trace_if.instr,
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i_compressed_i=trace_if.compressed,
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# apb interface
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i_paddr_i=apb.paddr,
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i_pwdata_i=apb.pwdata,
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i_pwrite_i=apb.pwrite,
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i_psel_i=apb.psel,
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i_penable_i=apb.penable,
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o_prdata_o=apb.prdata,
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o_pready_o=apb.pready,
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o_pslverr_o=apb.pslverr,
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# data output
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o_packet_word_o=source.data,
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o_packet_word_valid_o=source.valid,
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i_grant_i=source.ready,
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)
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self.specials += Instance("trace_debugger", **self.trace_params)
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@staticmethod
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def add_sources(platform):
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add_manifest_sources(platform, "cv32e40p_trace_manifest.flist")
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class DebugModule(Module):
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jtag_layout = [
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("tck", 1),
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("tms", 1),
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("trst", 1),
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("tdi", 1),
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("tdo", 1),
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]
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def __init__(self, pads=None):
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self.dmbus = wishbone.Interface()
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self.sbbus = wishbone.Interface()
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dmbus = Record(obi_layout)
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sbbus = Record(obi_layout)
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self.submodules.sbbus_conv = OBI2Wishbone(sbbus, self.sbbus)
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self.submodules.dmbus_conv = Wishbone2OBI(self.dmbus, dmbus)
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self.debug_req = Signal()
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self.ndmreset = Signal()
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tdo_i = Signal()
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tdo_o = Signal()
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tdo_oe = Signal()
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if pads is None:
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pads = Record(self.jtag_layout)
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self.pads = pads
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self.specials += Tristate(pads.tdo, tdo_o, tdo_oe, tdo_i)
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self.dm_params = dict(
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i_clk=ClockSignal(),
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i_rst_n=~ResetSignal(),
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o_ndmreset=self.ndmreset,
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o_debug_req=self.debug_req,
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# slave bus
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i_dm_req=dmbus.req,
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i_dm_we=dmbus.we,
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i_dm_addr=dmbus.addr,
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i_dm_be=dmbus.be,
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i_dm_wdata=dmbus.wdata,
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o_dm_rdata=dmbus.rdata,
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# master bus
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o_sb_req=sbbus.req,
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o_sb_addr=sbbus.addr,
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o_sb_we=sbbus.we,
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o_sb_wdata=sbbus.wdata,
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o_sb_be=sbbus.be,
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i_sb_gnt=sbbus.gnt,
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i_sb_rvalid=sbbus.rvalid,
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i_sb_rdata=sbbus.rdata,
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# jtag
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i_tck=pads.tck,
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i_tms=pads.tms,
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i_trst_n=pads.trst,
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i_tdi=pads.tdi,
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o_tdo=tdo_o,
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o_tdo_oe=tdo_oe,
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)
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self.comb += [
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dmbus.gnt.eq(dmbus.req),
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dmbus.rvalid.eq(dmbus.gnt),
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]
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self.specials += Instance("dm_wrap", **self.dm_params)
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@staticmethod
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def add_sources(platform):
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add_manifest_sources(platform, "cv32e40p_dm_manifest.flist")
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class CV32E40P(CPU):
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name = "cv32e40p"
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human_name = "CV32E40P"
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data_width = 32
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endianness = "little"
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gcc_triple = CPU_GCC_TRIPLE_RISCV32
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linker_output_format = "elf32-littleriscv"
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nop = "nop"
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io_regions = {0x80000000: 0x80000000} # origin, length
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has_fpu = ["full"]
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@property
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def gcc_flags(self):
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flags = GCC_FLAGS[self.variant]
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flags += "-D__cv32e40p__ "
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return flags
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def __init__(self, platform, variant="standard"):
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assert variant in CPU_VARIANTS, "Unsupported variant %s" % variant
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self.platform = platform
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self.variant = variant
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self.reset = Signal()
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self.ibus = wishbone.Interface()
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self.dbus = wishbone.Interface()
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self.periph_buses = [self.ibus, self.dbus]
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self.memory_buses = []
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self.interrupt = Signal(15)
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ibus = Record(obi_layout)
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dbus = Record(obi_layout)
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self.submodules.ibus_conv = OBI2Wishbone(ibus, self.ibus)
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self.submodules.dbus_conv = OBI2Wishbone(dbus, self.dbus)
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self.comb += [
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ibus.we.eq(0),
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ibus.be.eq(1111),
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]
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self.cpu_params = dict(
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i_clk_i=ClockSignal(),
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i_rst_ni=~ResetSignal(),
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i_clock_en_i=1,
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i_test_en_i=0,
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i_fregfile_disable_i=0,
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i_core_id_i=0,
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i_cluster_id_i=0,
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# ibus
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o_instr_req_o=ibus.req,
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i_instr_gnt_i=ibus.gnt,
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i_instr_rvalid_i=ibus.rvalid,
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o_instr_addr_o=ibus.addr,
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i_instr_rdata_i=ibus.rdata,
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# dbus
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o_data_req_o=dbus.req,
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i_data_gnt_i=dbus.gnt,
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i_data_rvalid_i=dbus.rvalid,
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o_data_we_o=dbus.we,
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o_data_be_o=dbus.be,
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o_data_addr_o=dbus.addr,
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o_data_wdata_o=dbus.wdata,
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i_data_rdata_i=dbus.rdata,
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# apu
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i_apu_master_gnt_i=0,
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i_apu_master_valid_i=0,
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# irq
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i_irq_sec_i=0,
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i_irq_software_i=0,
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i_irq_external_i=0,
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i_irq_fast_i=self.interrupt,
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i_irq_nmi_i=0,
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i_irq_fastx_i=0,
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# debug
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i_debug_req_i=0,
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# cpu control
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i_fetch_enable_i=1,
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)
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# add verilog sources
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add_manifest_sources(platform, 'cv32e40p_manifest.flist')
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if variant in self.has_fpu:
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self.cpu_params.update(p_FPU=1)
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add_manifest_sources(platform, 'cv32e40p_fpu_manifest.flist')
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def add_debug_module(self, dm):
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self.cpu_params.update(i_debug_req_i=dm.debug_req)
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self.cpu_params.update(i_rst_ni=~(ResetSignal() | dm.ndmreset))
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def add_trace_core(self, trace):
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trace_if = trace.trace_if
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self.cpu_params.update(
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o_ivalid_o=trace_if.ivalid,
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o_iexception_o=trace_if.iexception,
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o_interrupt_o=trace_if.interrupt,
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o_cause_o=trace_if.cause,
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o_tval_o=trace_if.tval,
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o_priv_o=trace_if.priv,
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o_iaddr_o=trace_if.iaddr,
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o_instr_o=trace_if.instr,
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o_compressed_o=trace_if.compressed,
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)
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def set_reset_address(self, reset_address):
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assert not hasattr(self, "reset_address")
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self.reset_address = reset_address
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self.cpu_params.update(i_boot_addr_i=Signal(32, reset=reset_address))
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def do_finalize(self):
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assert hasattr(self, "reset_address")
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self.specials += Instance("riscv_core", **self.cpu_params)
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@ -0,0 +1,112 @@
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.global main
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.global isr
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.global _start
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_start:
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j crt_init
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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.balign 256
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vector_table:
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j trap_entry # 0 unused
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j trap_entry # 1 unused
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j trap_entry # 2 unused
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j trap_entry # 3 software
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j trap_entry # 4 unused
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j trap_entry # 5 unused
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j trap_entry # 6 unused
|
||||
j trap_entry # 7 timer
|
||||
j trap_entry # 8 unused
|
||||
j trap_entry # 9 unused
|
||||
j trap_entry # 10 unused
|
||||
j trap_entry # 11 external
|
||||
j trap_entry # 12 unused
|
||||
j trap_entry # 13 unused
|
||||
j trap_entry # 14 unused
|
||||
j trap_entry # 15 unused
|
||||
j trap_entry # 16 firq0
|
||||
j trap_entry # 17 firq1
|
||||
j trap_entry # 18 firq2
|
||||
j trap_entry # 19 firq3
|
||||
j trap_entry # 20 firq4
|
||||
j trap_entry # 21 firq5
|
||||
j trap_entry # 22 firq6
|
||||
j trap_entry # 23 firq7
|
||||
j trap_entry # 24 firq8
|
||||
j trap_entry # 25 firq9
|
||||
j trap_entry # 26 firq10
|
||||
j trap_entry # 27 firq11
|
||||
j trap_entry # 28 firq12
|
||||
j trap_entry # 29 firq13
|
||||
j trap_entry # 30 firq14
|
||||
j trap_entry # 31 unused
|
||||
|
||||
.global trap_entry
|
||||
trap_entry:
|
||||
sw x1, - 1*4(sp)
|
||||
sw x5, - 2*4(sp)
|
||||
sw x6, - 3*4(sp)
|
||||
sw x7, - 4*4(sp)
|
||||
sw x10, - 5*4(sp)
|
||||
sw x11, - 6*4(sp)
|
||||
sw x12, - 7*4(sp)
|
||||
sw x13, - 8*4(sp)
|
||||
sw x14, - 9*4(sp)
|
||||
sw x15, -10*4(sp)
|
||||
sw x16, -11*4(sp)
|
||||
sw x17, -12*4(sp)
|
||||
sw x28, -13*4(sp)
|
||||
sw x29, -14*4(sp)
|
||||
sw x30, -15*4(sp)
|
||||
sw x31, -16*4(sp)
|
||||
addi sp,sp,-16*4
|
||||
call isr
|
||||
lw x1 , 15*4(sp)
|
||||
lw x5, 14*4(sp)
|
||||
lw x6, 13*4(sp)
|
||||
lw x7, 12*4(sp)
|
||||
lw x10, 11*4(sp)
|
||||
lw x11, 10*4(sp)
|
||||
lw x12, 9*4(sp)
|
||||
lw x13, 8*4(sp)
|
||||
lw x14, 7*4(sp)
|
||||
lw x15, 6*4(sp)
|
||||
lw x16, 5*4(sp)
|
||||
lw x17, 4*4(sp)
|
||||
lw x28, 3*4(sp)
|
||||
lw x29, 2*4(sp)
|
||||
lw x30, 1*4(sp)
|
||||
lw x31, 0*4(sp)
|
||||
addi sp,sp,16*4
|
||||
mret
|
||||
.text
|
||||
|
||||
|
||||
crt_init:
|
||||
la sp, _fstack + 4
|
||||
la a0, vector_table
|
||||
csrw mtvec, a0
|
||||
|
||||
bss_init:
|
||||
la a0, _fbss
|
||||
la a1, _ebss
|
||||
bss_loop:
|
||||
beq a0,a1,bss_done
|
||||
sw zero,0(a0)
|
||||
add a0,a0,4
|
||||
j bss_loop
|
||||
bss_done:
|
||||
|
||||
li a0, 0x7FFF0880 //7FFF0880 enable timer + external interrupt + fast interrupt sources (until mstatus.MIE is set, they will never trigger an interrupt)
|
||||
csrw mie,a0
|
||||
|
||||
j main
|
||||
infinit_loop:
|
||||
j infinit_loop
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
#ifndef CSR_DEFS__H
|
||||
#define CSR_DEFS__H
|
||||
|
||||
#define CSR_MSTATUS_MIE 0x8
|
||||
|
||||
#define CSR_IRQ_MASK 0xBC0
|
||||
#define CSR_IRQ_PENDING 0xFC0
|
||||
|
||||
#define CSR_DCACHE_INFO 0xCC0
|
||||
|
||||
#endif /* CSR_DEFS__H */
|
||||
|
|
@ -0,0 +1,40 @@
|
|||
#ifndef __IRQ_H
|
||||
#define __IRQ_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <system.h>
|
||||
#include <generated/csr.h>
|
||||
|
||||
static inline unsigned int irq_getie(void)
|
||||
{
|
||||
return (csrr(mstatus) & CSR_MSTATUS_MIE) != 0;
|
||||
}
|
||||
|
||||
static inline void irq_setie(unsigned int ie)
|
||||
{
|
||||
if(ie) csrs(mstatus,CSR_MSTATUS_MIE); else csrc(mstatus,CSR_MSTATUS_MIE);
|
||||
}
|
||||
|
||||
static inline unsigned int irq_getmask(void)
|
||||
{
|
||||
return 0; // FIXME
|
||||
}
|
||||
|
||||
static inline void irq_setmask(unsigned int mask)
|
||||
{
|
||||
// FIXME
|
||||
}
|
||||
|
||||
static inline unsigned int irq_pending(void)
|
||||
{
|
||||
return 0;// FIXME
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __IRQ_H */
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
#ifndef __SYSTEM_H
|
||||
#define __SYSTEM_H
|
||||
|
||||
#include <csr-defs.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
__attribute__((unused)) static void flush_cpu_icache(void)
|
||||
{
|
||||
// FIXME
|
||||
asm volatile("nop");
|
||||
}
|
||||
|
||||
__attribute__((unused)) static void flush_cpu_dcache(void)
|
||||
{
|
||||
// FIXME
|
||||
asm volatile("nop");
|
||||
}
|
||||
|
||||
void flush_l2_cache(void);
|
||||
|
||||
void busy_wait(unsigned int ms);
|
||||
|
||||
#define csrr(reg) ({ unsigned long __tmp; \
|
||||
asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \
|
||||
__tmp; })
|
||||
|
||||
#define csrw(reg, val) ({ \
|
||||
if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \
|
||||
asm volatile ("csrw " #reg ", %0" :: "i"(val)); \
|
||||
else \
|
||||
asm volatile ("csrw " #reg ", %0" :: "r"(val)); })
|
||||
|
||||
#define csrs(reg, bit) ({ \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
asm volatile ("csrrs x0, " #reg ", %0" :: "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrs x0, " #reg ", %0" :: "r"(bit)); })
|
||||
|
||||
#define csrc(reg, bit) ({ \
|
||||
if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \
|
||||
asm volatile ("csrrc x0, " #reg ", %0" :: "i"(bit)); \
|
||||
else \
|
||||
asm volatile ("csrrc x0, " #reg ", %0" :: "r"(bit)); })
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __SYSTEM_H */
|
||||
|
|
@ -62,6 +62,41 @@ void isr(void)
|
|||
*((unsigned int *)PLIC_CLAIM) = claim;
|
||||
}
|
||||
}
|
||||
#elif defined(__cv32e40p__)
|
||||
|
||||
#define FIRQ_OFFSET 16
|
||||
#define IRQ_MASK 0x7FFFFFFF
|
||||
#define INVINST 2
|
||||
#define ECALL 11
|
||||
#define RISCV_TEST
|
||||
|
||||
void isr(void)
|
||||
{
|
||||
unsigned int cause = csrr(mcause) & IRQ_MASK;
|
||||
|
||||
if (csrr(mcause) & 0x80000000) {
|
||||
#ifndef UART_POLLING
|
||||
if (cause == (UART_INTERRUPT+FIRQ_OFFSET)){
|
||||
uart_isr();
|
||||
}
|
||||
#endif
|
||||
} else {
|
||||
#ifdef RISCV_TEST
|
||||
int gp;
|
||||
asm volatile ("mv %0, gp" : "=r"(gp));
|
||||
printf("E %d\n", cause);
|
||||
if (cause == INVINST) {
|
||||
printf("Inv Instr\n");
|
||||
for(;;);
|
||||
}
|
||||
if (cause == ECALL) {
|
||||
printf("Ecall (gp: %d)\n", gp);
|
||||
csrw(mepc, csrr(mepc)+4);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
}
|
||||
|
||||
#else
|
||||
void isr(void)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -50,6 +50,7 @@ repos = [
|
|||
("pythondata-cpu-minerva", ("https://github.com/litex-hub/", False, True, None)),
|
||||
("pythondata-cpu-microwatt", ("https://github.com/litex-hub/", False, True, 0xa7859fb)),
|
||||
("pythondata-cpu-blackparrot", ("https://github.com/litex-hub/", False, True, None)),
|
||||
("pythondata-cpu-cv32e40p", ("https://github.com/litex-hub/", False, True, None)),
|
||||
]
|
||||
|
||||
repos = OrderedDict(repos)
|
||||
|
|
|
|||
Loading…
Reference in New Issue