build/xilinx: add support for edif/ngc files
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@ -1,3 +1,5 @@
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import os
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from litex.build.generic_platform import GenericPlatform
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from litex.build.xilinx import common, vivado, ise
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@ -7,6 +9,7 @@ class XilinxPlatform(GenericPlatform):
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def __init__(self, *args, toolchain="ise", **kwargs):
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GenericPlatform.__init__(self, *args, **kwargs)
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self.edifs = set()
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if toolchain == "ise":
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self.toolchain = ise.XilinxISEToolchain()
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elif toolchain == "vivado":
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@ -14,6 +17,9 @@ class XilinxPlatform(GenericPlatform):
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else:
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raise ValueError("Unknown toolchain")
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def add_edif(self, filename):
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self.edifs.add((os.path.abspath(filename)))
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def get_verilog(self, *args, special_overrides=dict(), **kwargs):
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so = dict(common.xilinx_special_overrides)
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if self.device[:3] == "xc7":
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@ -88,7 +88,7 @@ class XilinxVivadoToolchain:
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self.clocks = dict()
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self.false_paths = set()
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def _build_batch(self, platform, sources, build_name):
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def _build_batch(self, platform, sources, edifs, build_name):
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tcl = []
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tcl.append("create_property ars_ff cell")
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tcl.append("create_property ars_false_path net")
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@ -97,7 +97,9 @@ class XilinxVivadoToolchain:
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tcl.append("add_files " + filename_tcl)
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tcl.append("set_property library {} [get_files {}]"
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.format(library, filename_tcl))
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for filename in edifs:
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filename_tcl = "{" + filename + "}"
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tcl.append("read_edif " + filename_tcl)
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tcl.append("read_xdc {}.xdc".format(build_name))
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tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
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# "-include_dirs {}" crashes Vivado 2016.4
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@ -191,7 +193,8 @@ class XilinxVivadoToolchain:
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v_file = build_name + ".v"
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v_output.write(v_file)
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sources = platform.sources | {(v_file, "verilog", "work")}
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self._build_batch(platform, sources, build_name)
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edifs = platform.edifs
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self._build_batch(platform, sources, edifs, build_name)
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tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
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if run:
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_run_vivado(build_name, toolchain_path, source)
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