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build/xilinx: add support for edif/ngc files

This commit is contained in:
Florent Kermarrec 2017-12-16 13:20:45 +01:00
parent b31d0f37db
commit 4c82eb549f
2 changed files with 12 additions and 3 deletions
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6
litex/build/xilinx/platform.py
View File

@ -1,3 +1,5 @@
import os
from litex.build.generic_platform import GenericPlatform from litex.build.generic_platform import GenericPlatform
from litex.build.xilinx import common, vivado, ise from litex.build.xilinx import common, vivado, ise
@ -7,6 +9,7 @@ class XilinxPlatform(GenericPlatform):
def __init__(self, *args, toolchain="ise", **kwargs): def __init__(self, *args, toolchain="ise", **kwargs):
GenericPlatform.__init__(self, *args, **kwargs) GenericPlatform.__init__(self, *args, **kwargs)
self.edifs = set()
if toolchain == "ise": if toolchain == "ise":
self.toolchain = ise.XilinxISEToolchain() self.toolchain = ise.XilinxISEToolchain()
elif toolchain == "vivado": elif toolchain == "vivado":
@ -14,6 +17,9 @@ class XilinxPlatform(GenericPlatform):
else: else:
raise ValueError("Unknown toolchain") raise ValueError("Unknown toolchain")
def add_edif(self, filename):
self.edifs.add((os.path.abspath(filename)))
def get_verilog(self, *args, special_overrides=dict(), **kwargs): def get_verilog(self, *args, special_overrides=dict(), **kwargs):
so = dict(common.xilinx_special_overrides) so = dict(common.xilinx_special_overrides)
if self.device[:3] == "xc7": if self.device[:3] == "xc7":

9
litex/build/xilinx/vivado.py
View File

@ -88,7 +88,7 @@ class XilinxVivadoToolchain:
self.clocks = dict() self.clocks = dict()
self.false_paths = set() self.false_paths = set()
def _build_batch(self, platform, sources, build_name): def _build_batch(self, platform, sources, edifs, build_name):
tcl = [] tcl = []
tcl.append("create_property ars_ff cell") tcl.append("create_property ars_ff cell")
tcl.append("create_property ars_false_path net") tcl.append("create_property ars_false_path net")
@ -97,7 +97,9 @@ class XilinxVivadoToolchain:
tcl.append("add_files " + filename_tcl) tcl.append("add_files " + filename_tcl)
tcl.append("set_property library {} [get_files {}]" tcl.append("set_property library {} [get_files {}]"
.format(library, filename_tcl)) .format(library, filename_tcl))
for filename in edifs:
filename_tcl = "{" + filename + "}"
tcl.append("read_edif " + filename_tcl)
tcl.append("read_xdc {}.xdc".format(build_name)) tcl.append("read_xdc {}.xdc".format(build_name))
tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands) tcl.extend(c.format(build_name=build_name) for c in self.pre_synthesis_commands)
# "-include_dirs {}" crashes Vivado 2016.4 # "-include_dirs {}" crashes Vivado 2016.4
@ -191,7 +193,8 @@ class XilinxVivadoToolchain:
v_file = build_name + ".v" v_file = build_name + ".v"
v_output.write(v_file) v_output.write(v_file)
sources = platform.sources | {(v_file, "verilog", "work")} sources = platform.sources | {(v_file, "verilog", "work")}
self._build_batch(platform, sources, build_name) edifs = platform.edifs
self._build_batch(platform, sources, edifs, build_name)
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc)) tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc, named_pc))
if run: if run:
_run_vivado(build_name, toolchain_path, source) _run_vivado(build_name, toolchain_path, source)