Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

corelogic/record: empty default name

This commit is contained in:
Sebastien Bourdeauducq 2012-01-16 19:38:14 +01:00
parent bdde97f5fd
commit 4c85d921b3
1 changed files with 9 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
migen/corelogic/record.py
View File

@ -1,17 +1,21 @@
from migen.fhdl.structure import * from migen.fhdl.structure import *
class Record: class Record:
def __init__(self, layout, name=None): def __init__(self, layout, name=""):
self.name = name or "anonymous" self.name = name
self.field_order = [] self.field_order = []
if self.name:
prefix = self.name + "_"
else:
prefix = ""
for f in layout: for f in layout:
if isinstance(f, tuple): if isinstance(f, tuple):
if isinstance(f[1], BV): if isinstance(f[1], BV):
setattr(self, f[0], Signal(f[1], self.name + "_" + f[0])) setattr(self, f[0], Signal(f[1], prefix + f[0]))
elif isinstance(f[1], Signal) or isinstance(f[1], Record): elif isinstance(f[1], Signal) or isinstance(f[1], Record):
setattr(self, f[0], f[1]) setattr(self, f[0], f[1])
elif isinstance(f[1], list): elif isinstance(f[1], list):
setattr(self, f[0], Record(f[1], self.name + "_" + f[0])) setattr(self, f[0], Record(f[1], prefix + f[0]))
else: else:
raise TypeError raise TypeError
if len(f) == 3: if len(f) == 3:
@ -19,7 +23,7 @@ class Record:
else: else:
self.field_order.append((f[0], 1)) self.field_order.append((f[0], 1))
else: else:
setattr(self, f, Signal(BV(1), self.name + "_" + f)) setattr(self, f, Signal(BV(1), prefix + f))
self.field_order.append((f, 1)) self.field_order.append((f, 1))
def layout(self): def layout(self):