Merge pull request #423 from gsomlo/gls-ethmac-fixes

integration/soc: add_ethernet: honor self.map["ethmac"], if present
2020-03-11 12:33:50 +01:00 · 2020-03-11 12:33:50 +01:00 · 4ccf62afc1
parent bb8905fa5d a904034811
commit 4ccf62afc1
1 changed files with 2 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -1044,7 +1044,8 @@ class LiteXSoC(SoC):
            dw         = 32,
            interface  = "wishbone",
            endianness = self.cpu.endianness)
-        ethmac_region = SoCRegion(size=0x2000, cached=False)
+        ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None),
+                                  size=0x2000, cached=False)
        self.bus.add_slave(name="ethmac", slave=self.ethmac.bus, region=ethmac_region)
        self.add_csr("ethmac")
        self.add_interrupt("ethmac")