enjoy-digital
GitHub
commit
4cdd679908
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@ -9,10 +9,12 @@ class PicoRV32(Module):
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name = "picorv32"
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endianness = "little"
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gcc_triple = ("riscv64-unknown-elf", "riscv32-unknown-elf")
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gcc_flags = "-D__picorv32__ -mno-save-restore -march=rv32im -mabi=ilp32"
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gcc_flags_template = "-D__picorv32__ -mno-save-restore -march=rv32{ext} -mabi=ilp32"
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linker_output_format = "elf32-littleriscv"
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def __init__(self, platform, progaddr_reset, variant):
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self.gcc_flags = ""
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self.reset = Signal()
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self.ibus = i = wishbone.Interface()
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self.dbus = d = wishbone.Interface()
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@ -29,31 +31,53 @@ class PicoRV32(Module):
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mem_wstrb = Signal(4)
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mem_rdata = Signal(32)
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# PicoRV32 parameters. To create a new variant, modify this dictionary
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# and change the desired parameters.
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picorv32_params = {
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"p_ENABLE_COUNTERS" : 1,
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"p_ENABLE_COUNTERS64" : 1,
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# Changing REGS has no effect as on FPGAs, the registers are
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# implemented using a register file stored in DPRAM.
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"p_ENABLE_REGS_16_31" : 1,
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"p_ENABLE_REGS_DUALPORT" : 1,
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"p_LATCHED_MEM_RDATA" : 0,
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"p_TWO_STAGE_SHIFT" : 1,
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"p_TWO_CYCLE_COMPARE" : 0,
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"p_TWO_CYCLE_ALU" : 0,
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"p_CATCH_MISALIGN" : 1,
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"p_CATCH_ILLINSN" : 1,
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"p_ENABLE_PCPI" : 0,
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"p_ENABLE_MUL" : 1,
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"p_ENABLE_DIV" : 1,
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"p_ENABLE_FAST_MUL" : 0,
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"p_ENABLE_IRQ" : 1,
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"p_ENABLE_IRQ_QREGS" : 1,
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"p_ENABLE_IRQ_TIMER" : 1,
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"p_ENABLE_TRACE" : 0,
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"p_MASKED_IRQ" : 0x00000000,
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"p_LATCHED_IRQ" : 0xffffffff,
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"p_PROGADDR_RESET" : progaddr_reset,
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"p_PROGADDR_IRQ" : progaddr_reset + 0x00000010,
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"p_STACKADDR" : 0xffffffff
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}
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if variant == None:
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self.gcc_flags = PicoRV32.gcc_flags_template.format(ext="im")
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elif variant == "minimal":
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picorv32_params.update({
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"p_ENABLE_COUNTERS" : 0,
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"p_ENABLE_COUNTERS64" : 0,
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"p_TWO_STAGE_SHIFT" : 0,
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"p_CATCH_MISALIGN" : 0,
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"p_ENABLE_MUL" : 0,
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"p_ENABLE_DIV" : 0,
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"p_ENABLE_IRQ_TIMER" : 0
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})
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self.gcc_flags = PicoRV32.gcc_flags_template.format(ext="i")
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self.specials += Instance("picorv32",
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# parameters
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p_ENABLE_COUNTERS=1,
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p_ENABLE_COUNTERS64=1,
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p_ENABLE_REGS_16_31=1,
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p_ENABLE_REGS_DUALPORT=1,
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p_LATCHED_MEM_RDATA=0,
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p_TWO_STAGE_SHIFT=1,
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p_TWO_CYCLE_COMPARE=0,
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p_TWO_CYCLE_ALU=0,
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p_CATCH_MISALIGN=1,
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p_CATCH_ILLINSN=1,
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p_ENABLE_PCPI=0,
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p_ENABLE_MUL=1,
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p_ENABLE_DIV=1,
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p_ENABLE_FAST_MUL=0,
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p_ENABLE_IRQ=1,
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p_ENABLE_IRQ_QREGS=1,
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p_ENABLE_IRQ_TIMER=1,
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p_ENABLE_TRACE=0,
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p_MASKED_IRQ=0x00000000,
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p_LATCHED_IRQ=0xffffffff,
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p_PROGADDR_RESET=progaddr_reset,
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p_PROGADDR_IRQ=0x00000010,
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p_STACKADDR=0xffffffff,
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# parameters dictionary
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**picorv32_params,
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# clock / reset
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i_clk=ClockSignal(),
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@ -18,7 +18,23 @@ _start:
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.org 0x00000010 # IRQ
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_irq_vector:
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j _irq
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addi sp, sp, -16
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sw t0, 4(sp)
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sw ra, 8(sp)
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/* By convention, q2 holds true IRQ vector, but remains caller-save.
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We rely on the assumption that compiler-generated code will never touch
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the QREGs. q3 is truly scratch/caller-save. */
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picorv32_getq_insn(t0, q2)
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sw t0, 12(sp)
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jalr t0 // Call the true IRQ vector.
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lw t0, 12(sp)
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picorv32_setq_insn(q2, t0) // Restore the true IRQ vector.
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lw ra, 8(sp)
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lw t0, 4(sp)
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addi sp, sp, 16
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picorv32_retirq_insn() // return from interrupt
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/*
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@ -132,9 +148,7 @@ _irq:
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/* restore x1 - x2 from q registers */
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picorv32_getq_insn(x1, q1)
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picorv32_getq_insn(x2, q2)
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/* return from interrupt */
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picorv32_retirq_insn()
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ret
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/*
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* Reset handler, branched to from the vector.
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@ -180,9 +194,23 @@ _crt0:
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la t1, _irq_mask
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sw t0, 0(t1)
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/* Clear BSS */
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la t0, _fbss
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la t1, _ebss
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2:
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sw zero, 0(t0)
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addi t0, t0, 4
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bltu t0, t1, 2b
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/* set main stack */
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la sp, _fstack
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/* Set up address to IRQ handler since vector is hardcoded.
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By convention, q2 keeps the pointer to the true IRQ handler,
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to emulate relocatable interrupts. */
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la t0, _irq
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picorv32_setq_insn(q2, t0)
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/* jump to main */
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jal ra, main
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@ -206,7 +234,7 @@ _irq_enable:
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picorv32_maskirq_insn(zero, t0)
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ret
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/*
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/*
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* Disable interrupts by masking all interrupts (the mask should already be
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* up to date)
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*/
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@ -239,7 +267,7 @@ _irq_setmask:
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picorv32_maskirq_insn(zero, a0)
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1:
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ret
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.section .bss
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irq_regs:
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@ -272,4 +300,3 @@ _irq_mask:
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.global _irq_enabled
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_irq_enabled:
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.word 0
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