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software/bios: display SDRAM databits and freq.
This commit is contained in:
parent
6f69679d21
commit
4cf28a0107
3 changed files with 25 additions and 7 deletions
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@ -100,22 +100,29 @@ int main(int i, char **c)
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printf(" LiteX git sha1: "LITEX_GIT_SHA1"\n");
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printf(" LiteX git sha1: "LITEX_GIT_SHA1"\n");
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printf("\n");
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printf("\n");
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printf("--=============== \e[1mSoC\e[0m ==================--\n");
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printf("--=============== \e[1mSoC\e[0m ==================--\n");
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printf("\e[1mCPU\e[0m: %s @ %dMHz\n",
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printf("\e[1mCPU\e[0m:\t\t%s @ %dMHz\n",
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CONFIG_CPU_HUMAN_NAME,
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CONFIG_CPU_HUMAN_NAME,
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CONFIG_CLOCK_FREQUENCY/1000000);
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CONFIG_CLOCK_FREQUENCY/1000000);
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printf("\e[1mBUS\e[0m: %s %d-bit @ %dGiB\n",
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printf("\e[1mBUS\e[0m:\t\t%s %d-bit @ %dGiB\n",
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CONFIG_BUS_STANDARD,
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CONFIG_BUS_STANDARD,
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CONFIG_BUS_DATA_WIDTH,
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CONFIG_BUS_DATA_WIDTH,
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(1 << (CONFIG_BUS_ADDRESS_WIDTH - 30)));
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(1 << (CONFIG_BUS_ADDRESS_WIDTH - 30)));
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printf("\e[1mCSR\e[0m: %d-bit data\n",
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printf("\e[1mCSR\e[0m:\t\t%d-bit data\n",
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CONFIG_CSR_DATA_WIDTH);
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CONFIG_CSR_DATA_WIDTH);
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printf("\e[1mROM\e[0m: %dKiB\n", ROM_SIZE/1024);
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printf("\e[1mROM\e[0m:\t\t%dKiB\n", ROM_SIZE/1024);
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printf("\e[1mSRAM\e[0m: %dKiB\n", SRAM_SIZE/1024);
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printf("\e[1mSRAM\e[0m:\t\t%dKiB\n", SRAM_SIZE/1024);
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#ifdef CONFIG_L2_SIZE
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#ifdef CONFIG_L2_SIZE
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printf("\e[1mL2\e[0m: %dKiB\n", CONFIG_L2_SIZE/1024);
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printf("\e[1mL2\e[0m:\t\t%dKiB\n", CONFIG_L2_SIZE/1024);
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#endif
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#endif
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#ifdef MAIN_RAM_SIZE
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#ifdef MAIN_RAM_SIZE
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printf("\e[1mMAIN-RAM\e[0m: %dKiB\n", MAIN_RAM_SIZE/1024);
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#ifdef CSR_SDRAM_BASE
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printf("\e[1mSDRAM\e[0m:\t\t%dKiB %d-bit @ %dMHz\n",
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MAIN_RAM_SIZE/1024,
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sdrdatabits(),
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sdrfreq()/1000000);
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#else
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printf("\e[1mMAIN-RAM\e[0m:\t%dKiB \n", MAIN_RAM_SIZE/1024);
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#endif
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#endif
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#endif
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printf("\n");
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printf("\n");
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@ -42,6 +42,14 @@ __attribute__((unused)) static void cdelay(int i)
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#define DFII_PIX_DATA_BYTES DFII_PIX_DATA_SIZE*CSR_DATA_BYTES
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#define DFII_PIX_DATA_BYTES DFII_PIX_DATA_SIZE*CSR_DATA_BYTES
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int sdrdatabits(void) {
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return SDRAM_PHY_DATABITS;
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}
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int sdrfreq(void) {
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return SDRAM_PHY_XDR*SDRAM_PHY_PHASES*CONFIG_CLOCK_FREQUENCY;
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}
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void sdrsw(void)
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void sdrsw(void)
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{
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{
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sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
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sdram_dfii_control_write(DFII_CONTROL_CKE|DFII_CONTROL_ODT|DFII_CONTROL_RESET_N);
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@ -3,6 +3,9 @@
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#include <generated/csr.h>
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#include <generated/csr.h>
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int sdrdatabits(void);
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int sdrfreq(void);
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void sdrsw(void);
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void sdrsw(void);
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void sdrhw(void);
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void sdrhw(void);
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void sdrrow(unsigned int row);
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void sdrrow(unsigned int row);
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