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https://github.com/enjoy-digital/litex.git
synced 2025-01-04 09:52:26 -05:00
framebuffer: unpack memory words in pixel clock domain for better perf
This commit is contained in:
Sebastien Bourdeauducq
parent
8f164d0d7b
commit
4cfcda6c8c
3 changed files with 63 additions and 71 deletions
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@ -9,23 +9,20 @@ from misoclib.framebuffer.phy import Driver
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class Framebuffer(Module, AutoCSR):
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def __init__(self, pads_vga, pads_dvi, lasmim, simulation=False):
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pack_factor = lasmim.dw//(2*bpp)
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packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
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pack_factor = lasmim.dw//bpp
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self._enable = CSRStorage()
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self.fi = FrameInitiator()
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self.fi = FrameInitiator(pack_factor)
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self.dma = spi.DMAReadController(dma_lasmi.Reader(lasmim), spi.MODE_EXTERNAL, length_reset=640*480*4)
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self.driver = Driver(pads_vga, pads_dvi)
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self.driver = Driver(pack_factor, pads_vga, pads_dvi)
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cast = structuring.Cast(lasmim.dw, packed_pixels, reverse_to=True)
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unpack = structuring.Unpack(pack_factor, pixel_layout)
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vtg = VTG()
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cast = structuring.Cast(lasmim.dw, pixel_layout(pack_factor), reverse_to=True)
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vtg = VTG(pack_factor)
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g = DataFlowGraph()
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g.add_connection(self.fi, vtg, sink_ep="timing")
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g.add_connection(self.dma, cast)
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g.add_connection(cast, unpack)
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g.add_connection(unpack, vtg, sink_ep="pixels")
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g.add_connection(cast, vtg, sink_ep="pixels")
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g.add_connection(vtg, self.driver)
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self.submodules += CompositeActor(g)
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@ -36,10 +33,11 @@ class Framebuffer(Module, AutoCSR):
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]
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class Blender(PipelinedActor, AutoCSR):
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def __init__(self, nimages, latency):
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sink_layout = [("i"+str(i), pixel_layout) for i in range(nimages)]
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def __init__(self, nimages, pack_factor, latency):
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epixel_layout = pixel_layout(pack_factor)
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sink_layout = [("i"+str(i), epixel_layout) for i in range(nimages)]
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self.sink = Sink(sink_layout)
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self.source = Source(pixel_layout)
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self.source = Source(epixel_layout)
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factors = []
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for i in range(nimages):
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name = "f"+str(i)
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@ -54,8 +52,8 @@ class Blender(PipelinedActor, AutoCSR):
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self.sync += If(self.pipe_ce, sink_registered.eq(self.sink.payload))
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imgs = [getattr(sink_registered, "i"+str(i)) for i in range(nimages)]
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outval = Record(pixel_layout)
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for e in pixel_layout:
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outval = Record(epixel_layout)
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for e in epixel_layout:
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name = e[0]
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inpixs = [getattr(img, name) for img in imgs]
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outpix = getattr(outval, name)
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@ -74,7 +72,7 @@ class Blender(PipelinedActor, AutoCSR):
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pipe_stmts = []
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for i in range(latency-1):
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new_outval = Record(pixel_layout)
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new_outval = Record(epixel_layout)
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pipe_stmts.append(new_outval.eq(outval))
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outval = new_outval
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self.sync += If(self.pipe_ce, pipe_stmts)
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@ -82,29 +80,25 @@ class Blender(PipelinedActor, AutoCSR):
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class MixFramebuffer(Module, AutoCSR):
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def __init__(self, pads_vga, pads_dvi, *lasmims, blender_latency=5):
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pack_factor = lasmims[0].dw//(2*bpp)
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packed_pixels = structuring.pack_layout(pixel_layout, pack_factor)
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pack_factor = lasmims[0].dw//bpp
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self._enable = CSRStorage()
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self.fi = FrameInitiator()
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self.blender = Blender(len(lasmims), blender_latency)
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self.driver = Driver(pads_vga, pads_dvi)
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self.fi = FrameInitiator(pack_factor)
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self.blender = Blender(len(lasmims), pack_factor, blender_latency)
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self.driver = Driver(pack_factor, pads_vga, pads_dvi)
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self.comb += self.fi.trigger.eq(self._enable.storage)
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g = DataFlowGraph()
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epixel_layout = pixel_layout(pack_factor)
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for n, lasmim in enumerate(lasmims):
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dma = spi.DMAReadController(dma_lasmi.Reader(lasmim), spi.MODE_EXTERNAL, length_reset=640*480*4)
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cast = structuring.Cast(lasmim.dw, packed_pixels, reverse_to=True)
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unpack = structuring.Unpack(pack_factor, pixel_layout)
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cast = structuring.Cast(lasmim.dw, epixel_layout, reverse_to=True)
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g.add_connection(dma, cast)
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g.add_connection(cast, unpack)
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g.add_connection(unpack, self.blender, sink_subr=["i"+str(n)])
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g.add_connection(cast, self.blender, sink_subr=["i"+str(n)])
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self.comb += dma.generator.trigger.eq(self._enable.storage)
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setattr(self, "dma"+str(n), dma)
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vtg = VTG()
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vtg = VTG(pack_factor)
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self.comb += vtg.enable.eq(self._enable.storage)
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g.add_connection(self.fi, vtg, sink_ep="timing")
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g.add_connection(self.blender, vtg, sink_ep="pixels")
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@ -3,7 +3,7 @@ from migen.flow.actor import *
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from migen.bank.description import CSRStorage
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from migen.actorlib import spi
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_hbits = 11
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_hbits = 12
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_vbits = 12
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bpp = 32
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@ -14,10 +14,8 @@ pixel_layout_s = [
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("g", bpc),
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("b", bpc)
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]
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pixel_layout = [
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("p0", pixel_layout_s),
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("p1", pixel_layout_s)
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]
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def pixel_layout(pack_factor):
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return [("p"+str(i), pixel_layout_s) for i in range(pack_factor)]
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bpc_phy = 8
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phy_layout_s = [
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@ -25,21 +23,21 @@ phy_layout_s = [
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("g", bpc_phy),
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("b", bpc_phy)
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]
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phy_layout = [
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("hsync", 1),
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("vsync", 1),
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("de", 1),
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("p0", phy_layout_s),
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("p1", phy_layout_s)
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]
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def phy_layout(pack_factor):
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r = [("hsync", 1), ("vsync", 1), ("de", 1)]
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for i in range(pack_factor):
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r.append(("p"+str(i), phy_layout_s))
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return r
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class FrameInitiator(spi.SingleGenerator):
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def __init__(self):
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def __init__(self, pack_factor):
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h_alignment_bits = log2_int(pack_factor)
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hbits_dyn = _hbits - h_alignment_bits
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layout = [
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("hres", _hbits, 640, 1),
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("hsync_start", _hbits, 656, 1),
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("hsync_end", _hbits, 752, 1),
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("hscan", _hbits, 800, 1),
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("hres", hbits_dyn, 640, h_alignment_bits),
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("hsync_start", hbits_dyn, 656, h_alignment_bits),
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("hsync_end", hbits_dyn, 752, h_alignment_bits),
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("hscan", hbits_dyn, 800, h_alignment_bits),
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("vres", _vbits, 480),
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("vsync_start", _vbits, 492),
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@ -49,19 +47,20 @@ class FrameInitiator(spi.SingleGenerator):
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spi.SingleGenerator.__init__(self, layout, spi.MODE_EXTERNAL)
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class VTG(Module):
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def __init__(self):
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def __init__(self, pack_factor):
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hbits_dyn = _hbits - log2_int(pack_factor)
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self.enable = Signal()
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self.timing = Sink([
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("hres", _hbits),
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("hsync_start", _hbits),
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("hsync_end", _hbits),
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("hscan", _hbits),
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("hres", hbits_dyn),
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("hsync_start", hbits_dyn),
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("hsync_end", hbits_dyn),
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("hscan", hbits_dyn),
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("vres", _vbits),
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("vsync_start", _vbits),
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("vsync_end", _vbits),
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("vscan", _vbits)])
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self.pixels = Sink(pixel_layout)
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self.phy = Source(phy_layout)
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self.pixels = Sink(pixel_layout(pack_factor))
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self.phy = Source(phy_layout(pack_factor))
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self.busy = Signal()
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###
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@ -71,7 +70,7 @@ class VTG(Module):
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active = Signal()
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generate_en = Signal()
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hcounter = Signal(_hbits)
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hcounter = Signal(hbits_dyn)
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vcounter = Signal(_vbits)
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skip = bpc - bpc_phy
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@ -79,7 +78,7 @@ class VTG(Module):
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active.eq(hactive & vactive),
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If(active,
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[getattr(getattr(self.phy.payload, p), c).eq(getattr(getattr(self.pixels.payload, p), c)[skip:])
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for p in ["p0", "p1"] for c in ["r", "g", "b"]],
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for p in ["p"+str(i) for i in range(pack_factor)] for c in ["r", "g", "b"]],
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self.phy.payload.de.eq(1)
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),
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@ -8,8 +8,8 @@ from misoclib.framebuffer.format import bpc_phy, phy_layout
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from misoclib.framebuffer import dvi
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class _FIFO(Module):
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def __init__(self):
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self.phy = Sink(phy_layout)
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def __init__(self, pack_factor):
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self.phy = Sink(phy_layout(pack_factor))
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self.busy = Signal()
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self.pix_hsync = Signal()
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@ -21,7 +21,7 @@ class _FIFO(Module):
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###
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fifo = RenameClockDomains(AsyncFIFO(phy_layout, 512),
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fifo = RenameClockDomains(AsyncFIFO(phy_layout(pack_factor), 512),
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{"write": "sys", "read": "pix"})
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self.submodules += fifo
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self.comb += [
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@ -31,23 +31,22 @@ class _FIFO(Module):
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self.busy.eq(0)
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]
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pix_parity = Signal()
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unpack_counter = Signal(max=pack_factor)
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assert(pack_factor & (pack_factor - 1) == 0) # only support powers of 2
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self.sync.pix += [
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pix_parity.eq(~pix_parity),
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unpack_counter.eq(unpack_counter + 1),
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self.pix_hsync.eq(fifo.dout.hsync),
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self.pix_vsync.eq(fifo.dout.vsync),
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self.pix_de.eq(fifo.dout.de),
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If(pix_parity,
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self.pix_r.eq(fifo.dout.p1.r),
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self.pix_g.eq(fifo.dout.p1.g),
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self.pix_b.eq(fifo.dout.p1.b)
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).Else(
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self.pix_r.eq(fifo.dout.p0.r),
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self.pix_g.eq(fifo.dout.p0.g),
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self.pix_b.eq(fifo.dout.p0.b)
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)
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self.pix_de.eq(fifo.dout.de)
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]
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self.comb += fifo.re.eq(pix_parity)
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for i in range(pack_factor):
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pixel = getattr(fifo.dout, "p"+str(i))
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self.sync.pix += If(unpack_counter == i,
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self.pix_r.eq(pixel.r),
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self.pix_g.eq(pixel.g),
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self.pix_b.eq(pixel.b)
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)
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self.comb += fifo.re.eq(unpack_counter == (pack_factor - 1))
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# This assumes a 50MHz base clock
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class _Clocking(Module, AutoCSR):
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@ -168,8 +167,8 @@ class _Clocking(Module, AutoCSR):
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o_O=pads_dvi.clk_p, o_OB=pads_dvi.clk_n)
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class Driver(Module, AutoCSR):
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def __init__(self, pads_vga, pads_dvi):
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fifo = _FIFO()
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def __init__(self, pack_factor, pads_vga, pads_dvi):
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fifo = _FIFO(pack_factor)
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self.submodules += fifo
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self.phy = fifo.phy
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self.busy = fifo.busy
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