verilog: break down Convert function
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26e0b817e8
commit
4d6be55e9f
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@ -78,6 +78,62 @@ def _printnode(ns, is_sync, level, node):
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else:
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else:
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raise TypeError
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raise TypeError
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def _printheader(f, ios, name, ns):
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sigs = list_signals(f)
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targets = list_targets(f)
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instouts = list_inst_outs(f)
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r = "module " + name + "(\n"
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firstp = True
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for sig in ios:
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if not firstp:
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r += ",\n"
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firstp = False
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if sig in targets:
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r += "\toutput reg " + _printsig(ns, sig)
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elif sig in instouts:
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r += "\toutput " + _printsig(ns, sig)
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else:
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r += "\tinput " + _printsig(ns, sig)
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r += "\n);\n\n"
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for sig in sigs - ios:
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if sig in instouts:
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r += "wire " + _printsig(ns, sig) + ";\n"
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else:
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r += "reg " + _printsig(ns, sig) + ";\n"
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r += "\n"
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return r
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def _printcomb(f, ns):
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r = ""
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if f.comb.l:
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# Generate a dummy event to get the simulator
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# to run the combinatorial process once at the beginning.
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syn_off = "// synthesis translate off\n"
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syn_on = "// synthesis translate on\n"
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dummy_s = Signal(name="dummy_s")
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dummy_d = Signal(name="dummy_d")
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r += syn_off
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r += "reg " + _printsig(ns, dummy_s) + ";\n"
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r += "reg " + _printsig(ns, dummy_d) + ";\n"
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r += "initial " + ns.get_name(dummy_s) + " <= 1'b0;\n"
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r += syn_on + "\n"
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r += "always @(*) begin\n"
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r += _printnode(ns, False, 1, f.comb)
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r += syn_off
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r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
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r += syn_on
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r += "end\n\n"
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return r
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def _printsync(f, ns, clk_signal, rst_signal):
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r = ""
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if f.sync.l:
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r += "always @(posedge " + ns.get_name(clk_signal) + ") begin\n"
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r += _printnode(ns, True, 1, insert_reset(rst_signal, f.sync))
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r += "end\n\n"
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return r
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def _printinstances(ns, i, clk, rst):
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def _printinstances(ns, i, clk, rst):
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r = ""
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r = ""
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for x in i:
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for x in i:
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@ -116,7 +172,7 @@ def _printinstances(ns, i, clk, rst):
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r += "\n"
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r += "\n"
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r += ");\n\n"
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r += ");\n\n"
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return r
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return r
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def Convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, ns=None):
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def Convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, ns=None):
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if clk_signal is None:
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if clk_signal is None:
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clk_signal = Signal(name="sys_clk")
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clk_signal = Signal(name="sys_clk")
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@ -128,55 +184,11 @@ def Convert(f, ios=set(), name="top", clk_signal=None, rst_signal=None, ns=None)
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ns = Namespace()
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ns = Namespace()
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ios |= f.pads
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ios |= f.pads
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sigs = list_signals(f)
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targets = list_targets(f)
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instouts = list_inst_outs(f)
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r = "/* Machine-generated using Migen */\n"
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r = "/* Machine-generated using Migen */\n"
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r += "module " + name + "(\n"
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r += _printheader(f, ios, name, ns)
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firstp = True
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r += _printcomb(f, ns)
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for sig in ios:
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r += _printsync(f, ns, clk_signal, rst_signal)
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if not firstp:
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r += ",\n"
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firstp = False
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if sig in targets:
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r += "\toutput reg " + _printsig(ns, sig)
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elif sig in instouts:
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r += "\toutput " + _printsig(ns, sig)
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else:
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r += "\tinput " + _printsig(ns, sig)
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r += "\n);\n\n"
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for sig in sigs - ios:
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if sig in instouts:
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r += "wire " + _printsig(ns, sig) + ";\n"
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else:
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r += "reg " + _printsig(ns, sig) + ";\n"
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r += "\n"
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if f.comb.l:
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# Generate a dummy event to get the simulator
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# to run the combinatorial process once at the beginning.
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syn_off = "// synthesis translate off\n"
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syn_on = "// synthesis translate on\n"
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dummy_s = Signal(name="dummy_s")
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dummy_d = Signal(name="dummy_d")
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r += syn_off
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r += "reg " + _printsig(ns, dummy_s) + ";\n"
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r += "reg " + _printsig(ns, dummy_d) + ";\n"
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r += "initial " + ns.get_name(dummy_s) + " <= 1'b0;\n"
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r += syn_on + "\n"
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r += "always @(*) begin\n"
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r += _printnode(ns, False, 1, f.comb)
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r += syn_off
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r += "\t" + ns.get_name(dummy_d) + " <= " + ns.get_name(dummy_s) + ";\n"
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r += syn_on
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r += "end\n\n"
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if f.sync.l:
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r += "always @(posedge " + ns.get_name(clk_signal) + ") begin\n"
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r += _printnode(ns, True, 1, insert_reset(rst_signal, f.sync))
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r += "end\n\n"
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r += _printinstances(ns, f.instances, clk_signal, rst_signal)
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r += _printinstances(ns, f.instances, clk_signal, rst_signal)
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r += "endmodule\n"
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r += "endmodule\n"
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