soc/core/xadc: cleanup, simplify and add expose_drp method - keep CSR ordering with older version, requested for software compatibility. - always enable analog capability (user will just not use it if not needed). - add expose_drp method (similar to clock.py) for cases where DRP is needed.
This commit is contained in:
Florent Kermarrec
bunnie
parent
5eec7432b8
commit
4dc0a61428
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@ -1,4 +1,6 @@
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# Copyright 2014-2015 Robert Jordens <jordens@gmail.com>
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# This file is Copyright (c) 2014-2015 Robert Jordens <jordens@gmail.com>
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# This file is Copyright (c) 2019 bunnie <bunnie@kosagi.com>
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# This file is Copyright (c) 2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen import *
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@ -7,76 +9,45 @@ from litex.soc.interconnect.csr import *
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# XADC ---------------------------------------------------------------------------------------------
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analog_layout = [("vauxp", 16), ("vauxn", 16), ("vp", 1), ("vn", 1)]
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class XADC(Module, AutoCSR):
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def __init__(self, analog=None):
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# add a CSR bank for controlling the XADC DRP. Adds bloat to the gateware
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# if you're not using this feature, but makes the code more elegant.
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self.drp_enable = CSRStorage() # must set this to 1 to use DRP, otherwise auto-sample
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self.drp_read = CSR()
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self.drp_write = CSR()
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self.drp_drdy = CSRStatus()
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self.drp_adr = CSRStorage(7)
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self.drp_dat_w = CSRStorage(16)
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self.drp_dat_r = CSRStatus(16)
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# monitor EOC/EOS so we can poll if the ADC has been updated
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self.eoc = CSRStatus()
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self.eos = CSRStatus()
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# TODO: hook up the alarm as interrupt
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drp_drdy = Signal()
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if analog == None:
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analog = Record(analog_layout)
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self.comb += [
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analog.vauxp.eq(0),
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analog.vauxn.eq(0),
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analog.vp.eq(0),
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analog.vn.eq(0),
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]
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self.sync += [
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If(self.drp_read.re | self.drp_write.re,
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self.drp_drdy.status.eq(0)
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).Elif(drp_drdy,
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self.drp_drdy.status.eq(1)
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)
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]
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def __init__(self):
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# Temperature(°C) = adc_value*503.975/4096 - 273.15
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self.temperature = CSRStatus(12)
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# Voltage(V) = as uadc_value*)/4096*3
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# Voltage(V) = adc_value*)/4096*3
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self.vccint = CSRStatus(12)
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self.vccaux = CSRStatus(12)
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self.vccbram = CSRStatus(12)
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# End of Convertion/Sequence
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self.eoc = CSRStatus()
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self.eos = CSRStatus()
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# Alarms
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self.alarm = Signal(8)
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self.ot = Signal()
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# Analog
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self.analog = Record([("vauxp", 16), ("vauxn", 16), ("vp", 1), ("vn", 1)])
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self.analog.vauxp.reset = 1
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self.analog.vp.reset = 1
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# # #
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busy = Signal()
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channel = Signal(7)
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eoc = Signal()
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eos = Signal()
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data = Signal(16)
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auto = Signal()
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self.comb += auto.eq(~self.drp_enable.storage)
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adr = Signal(7)
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self.comb += [
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If(auto,
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adr.eq(channel),
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).Else(
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adr.eq(self.drp_adr.storage)
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)
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]
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# XADC instance ----------------------------------------------------------------------------
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self.dwe = Signal()
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self.den = Signal()
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self.drdy = Signal()
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self.dadr = Signal(7)
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self.di = Signal(16)
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self.do = Signal(16)
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self.specials += Instance("XADC",
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# from ug480
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# From ug480
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p_INIT_40=0x9000, p_INIT_41=0x2ef0, p_INIT_42=0x0400,
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p_INIT_48=0x4701, p_INIT_49=0x000f,
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p_INIT_4A=0x4700, p_INIT_4B=0x0000,
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@ -87,39 +58,77 @@ class XADC(Module, AutoCSR):
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p_INIT_54=0xa93a, p_INIT_55=0x5111,
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p_INIT_56=0x91eb, p_INIT_57=0xae4e,
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p_INIT_58=0x5999, p_INIT_5C=0x5111,
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o_ALM=self.alarm, o_OT=self.ot,
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o_BUSY=busy, o_CHANNEL=channel, o_EOC=eoc, o_EOS=eos,
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i_VAUXN=analog.vauxn, i_VAUXP=analog.vauxp, i_VN=analog.vn, i_VP=analog.vp,
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i_CONVST=0, i_CONVSTCLK=0, i_RESET=ResetSignal(),
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o_DO=data, o_DRDY=drp_drdy, i_DADDR=adr, i_DCLK=ClockSignal(),
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i_DEN=(auto & eoc) | (~auto & (self.drp_read.re | self.drp_write.re)),
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i_DI=self.drp_dat_w.storage, i_DWE=self.drp_write.re,
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# o_JTAGBUSY=, o_JTAGLOCKED=, o_JTAGMODIFIED=, o_MUXADDR=,
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)
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self.sync += [
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If(drp_drdy,
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self.drp_dat_r.status.eq(data),
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).Else(
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self.drp_dat_r.status.eq(self.drp_dat_r.status),
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o_ALM = self.alarm,
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o_OT = self.ot,
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o_BUSY = busy,
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o_CHANNEL = channel,
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o_EOC = eoc,
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o_EOS = eos,
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i_VAUXN = self.analog.vauxn,
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i_VAUXP = self.analog.vauxp,
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i_VN = self.analog.vn,
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i_VP = self.analog.vp,
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i_CONVST = 0,
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i_CONVSTCLK = 0,
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i_RESET = ResetSignal(),
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i_DCLK = ClockSignal(),
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i_DWE = self.dwe,
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i_DEN = self.den,
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o_DRDY = self.drdy,
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i_DADDR = self.dadr,
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i_DI = self.di,
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o_DO = self.do
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)
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self.comb += [
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self.den.eq(eoc),
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self.dadr.eq(channel),
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]
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self.sync += [
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self.eoc.status.eq((~self.eoc.we & self.eoc.status) | eoc),
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self.eos.status.eq((~self.eos.we & self.eos.status) | eos),
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]
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# Channels update --------------------------------------------------------------------------
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channels = {
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0: self.temperature,
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1: self.vccint,
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2: self.vccaux,
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6: self.vccbram
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}
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self.sync += [
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If(drp_drdy & auto,
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If(self.drdy,
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Case(channel, dict(
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(k, v.status.eq(data >> 4))
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(k, v.status.eq(self.do >> 4))
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for k, v in channels.items()))
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)
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]
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# End of Convertion/Sequence update --------------------------------------------------------
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self.sync += [
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self.eoc.status.eq((self.eoc.status & ~self.eoc.we) | eoc),
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self.eos.status.eq((self.eos.status & ~self.eos.we) | eos),
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]
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def expose_drp(self):
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self.drp_enable = CSRStorage() # Set to 1 to use DRP and disable auto-sampling
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self.drp_read = CSR()
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self.drp_write = CSR()
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self.drp_drdy = CSRStatus()
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self.drp_adr = CSRStorage(7)
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self.drp_dat_w = CSRStorage(16)
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self.drp_dat_r = CSRStatus(16)
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# # #
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self.comb += [
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self.dwe.eq(self.drp_write.re),
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self.di.eq(self.drp_dat_w.storage),
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self.drp_dat_r.status.eq(self.do),
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If(self.drp_enable.storage,
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self.den.eq(self.drp_read.re | self.drp_write.re),
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self.dadr.eq(self.drp_adr.storage),
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),
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]
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self.sync += [
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If(self.drp_read.re | self.drp_write.re,
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self.drp_drdy.status.eq(0)
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).Elif(self.drdy,
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self.drp_drdy.status.eq(1)
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)
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]
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