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cores/uart: expose fsm/timer (to ease probing with LiteScope).

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This commit is contained in:
Florent Kermarrec 2021-01-25 12:29:18 +01:00
parent 17195c5e96
commit 4df336341b
1 changed files with 2 additions and 3 deletions
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5
litex/soc/cores/uart.py
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@ -273,10 +273,9 @@ class Stream2Wishbone(Module):
bytes_count_done = (bytes_count == (data_width//8 - 1)) bytes_count_done = (bytes_count == (data_width//8 - 1))
words_count_done = (words_count == (length - 1)) words_count_done = (words_count == (length - 1))
fsm = ResetInserter()(FSM(reset_state="RECEIVE-CMD")) self.submodules.fsm = fsm = ResetInserter()(FSM(reset_state="RECEIVE-CMD"))
timer = WaitTimer(int(100e-3*clk_freq)) self.submodules.timer = timer = WaitTimer(int(100e-3*clk_freq))
self.comb += timer.wait.eq(~fsm.ongoing("RECEIVE-CMD")) self.comb += timer.wait.eq(~fsm.ongoing("RECEIVE-CMD"))
self.submodules += fsm, timer
self.comb += fsm.reset.eq(timer.done) self.comb += fsm.reset.eq(timer.done)
fsm.act("RECEIVE-CMD", fsm.act("RECEIVE-CMD",
sink.ready.eq(1), sink.ready.eq(1),