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add an option to generate without reg initializers (asic targets) 

ASIC targets can't set a reg to a known value on boot, so for
more accurate simulations it would be nice to have an option
in the platform to specify generating the verilog without 'reg'
initializers. The presence of these initializers can mask
problems in simulations with X-prop that can lead to missing
explicit reset conditions.
This commit is contained in:
bunnie 2023-05-15 18:45:10 +08:00
parent 782f045b16
commit 4e15fd54b0
1 changed files with 8 additions and 3 deletions
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11
litex/gen/fhdl/verilog.py
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@ -421,7 +421,7 @@ def _print_module(f, ios, name, ns, attr_translate):
return r
def _print_signals(f, ios, name, ns, attr_translate):
def _print_signals(f, ios, name, ns, attr_translate, asic=False):
sigs = list_signals(f) | list_special_ios(f, ins=True, outs=True, inouts=True)
special_outs = list_special_ios(f, ins=False, outs=True, inouts=True)
inouts = list_special_ios(f, ins=False, outs=False, inouts=True)
@ -434,7 +434,10 @@ def _print_signals(f, ios, name, ns, attr_translate):
if sig in wires:
r += "wire " + _print_signal(ns, sig) + ";\n"
else:
r += "reg " + _print_signal(ns, sig) + " = " + _print_expression(ns, sig.reset)[0] + ";\n"
if asic:
r += "reg " + _print_signal(ns, sig) + ";\n" # ASICs can't assign an initial value to a reg, it is always X
else:
r += "reg " + _print_signal(ns, sig) + " = " + _print_expression(ns, sig.reset)[0] + ";\n"
return r
# ------------------------------------------------------------------------------------------------ #
@ -532,6 +535,8 @@ def convert(f, ios=set(), name="top", platform=None,
# Sim parameters.
time_unit = "1ns",
time_precision = "1ps",
# Generate for ASIC simulation (i.e. capture X-on-init for regs)
asic = False,
):
# Build Logic.
@ -618,7 +623,7 @@ def convert(f, ios=set(), name="top", platform=None,
# Module Signals.
verilog += _print_separator("Signals")
verilog += _print_signals(f, ios, name, ns, attr_translate)
verilog += _print_signals(f, ios, name, ns, attr_translate, asic)
# Combinatorial Logic.
verilog += _print_separator("Combinatorial Logic")