cores/spi/spi_bone: Cosmetic cleanups on FSM (rename states).
This commit is contained in:
Florent Kermarrec
parent
bdfb032be9
commit
4e8e97a22a
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@ -188,13 +188,13 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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# Signals.
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# --------
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count = Signal(8)
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offset = Signal(5)
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command = Signal(8)
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address = Signal(32)
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value = Signal(32)
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write = Signal()
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sync_byte = Signal(8)
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count = Signal(8)
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offset = Signal(5)
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synchro = Signal(8)
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command = Signal(8)
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address = Signal(32)
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data = Signal(32)
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write = Signal()
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# FSM.
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# ----
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@ -203,10 +203,10 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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self.submodules += fsm
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self.comb += fsm.reset.eq(cs_n)
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# Connect the Wishbone bus up to our values.
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# Connect the Wishbone bus up to our datas.
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self.comb += [
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bus.adr.eq(address[2:]),
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bus.dat_w.eq(value),
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bus.dat_w.eq(data),
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bus.sel.eq(2**len(bus.sel) - 1)
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]
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@ -224,10 +224,10 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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miso_en.eq(0),
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NextValue(miso, 1),
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If(clk_posedge,
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NextValue(sync_byte, Cat(mosi, sync_byte))
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NextValue(synchro, Cat(mosi, synchro))
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),
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If(sync_byte[0:7] == 0b101011,
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NextState("GET_TYPE_BYTE"),
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If(synchro[0:7] == 0b101011,
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NextState("GET-COMMAND"),
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NextValue(count, 0),
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NextValue(command, mosi)
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)
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@ -237,25 +237,25 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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miso_en.eq(0),
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NextValue(miso, 1),
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If(clk_posedge,
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NextState("GET_TYPE_BYTE"),
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NextState("GET-COMMAND"),
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NextValue(command, mosi)
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)
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)
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# Determine if it's a read or a write
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fsm.act("GET_TYPE_BYTE",
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fsm.act("GET-COMMAND",
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miso_en.eq(0),
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NextValue(miso, 1),
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If(count == 8,
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# Write value
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# Write data
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If(command == 0,
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NextValue(write, 1),
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NextState("READ_ADDRESS")
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NextState("GET-ADDRESS")
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# Read value
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# Read data
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).Elif(command == 1,
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NextValue(write, 0),
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NextState("READ_ADDRESS")
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NextState("GET-ADDRESS")
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).Else(
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NextState("END")
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),
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@ -265,13 +265,13 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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)
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)
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fsm.act("READ_ADDRESS",
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fsm.act("GET-ADDRESS",
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miso_en.eq(0),
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If(count == (32 + 8),
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If(write,
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NextState("READ_VALUE"),
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NextState("GET-DATA"),
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).Else(
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NextState("READ_WISHBONE"),
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NextState("BUS-MMAP-READ"),
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)
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),
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If(clk_posedge,
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@ -279,69 +279,69 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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)
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)
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fsm.act("READ_VALUE",
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fsm.act("GET-DATA",
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miso_en.eq(0),
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If(count == (32 + 32 + 8),
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NextState("WRITE_WISHBONE"),
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NextState("BUS-MMAP-WRITE"),
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),
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If(clk_posedge,
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NextValue(value, Cat(mosi, value))
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NextValue(data, Cat(mosi, data))
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)
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)
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fsm.act("WRITE_WISHBONE",
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fsm.act("BUS-MMAP-WRITE",
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bus.stb.eq(1),
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bus.we.eq(1),
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bus.cyc.eq(1),
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miso_en.eq(1),
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If(bus.ack | bus.err,
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NextState("WAIT_BYTE_BOUNDARY")
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NextState("WAIT-BYTE-BOUNDARY")
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)
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)
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fsm.act("READ_WISHBONE",
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fsm.act("BUS-MMAP-READ",
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bus.stb.eq(1),
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bus.we.eq(0),
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bus.cyc.eq(1),
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miso_en.eq(1),
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If(bus.ack | bus.err,
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NextState("WAIT_BYTE_BOUNDARY"),
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NextValue(value, bus.dat_r)
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NextState("WAIT-BYTE-BOUNDARY"),
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NextValue(data, bus.dat_r)
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)
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)
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fsm.act("WAIT_BYTE_BOUNDARY",
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fsm.act("WAIT-BYTE-BOUNDARY",
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miso_en.eq(1),
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If(clk_negedge,
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If(count[0:3] == 0,
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NextValue(miso, 0),
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# For writes, fill in the 0 byte response
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If(write,
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NextState("WRITE_WR_RESPONSE"),
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NextState("WRITE-WR-RESPONSE"),
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).Else(
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NextState("WRITE_RESPONSE"),
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NextState("WRITE-RESPONSE"),
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)
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)
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)
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)
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# Write the "01" byte that indicates a response
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fsm.act("WRITE_RESPONSE",
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fsm.act("WRITE-RESPONSE",
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miso_en.eq(1),
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If(clk_negedge,
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If(count[0:3] == 0b111,
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NextValue(miso, 1),
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).Elif(count[0:3] == 0,
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NextValue(offset, 31),
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NextState("WRITE_VALUE")
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NextState("WRITE-DATA")
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)
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)
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)
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# Write the actual value
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fsm.act("WRITE_VALUE",
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# Write the actual data
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fsm.act("WRITE-DATA",
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miso_en.eq(1),
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NextValue(miso, value >> offset),
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NextValue(miso, data >> offset),
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If(clk_negedge,
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NextValue(offset, offset - 1),
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If(offset == 0,
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@ -351,7 +351,7 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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)
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)
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fsm.act("WRITE_WR_RESPONSE",
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fsm.act("WRITE-WR-RESPONSE",
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miso_en.eq(1),
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If(clk_negedge,
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If(count[0:3] == 0,
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@ -363,7 +363,7 @@ class SPIBone(Module, ModuleDoc, AutoDoc):
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if wires in [2]:
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fsm.act("END",
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miso_en.eq(0),
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NextValue(sync_byte, 0),
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NextValue(synchro, 0),
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NextState("IDLE")
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)
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if wires in [3, 4]:
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