gen/fhdl/specials: revert migen's commit d98502c6 (specials/Memory: homogenize read-only port syntax) since causing a regression with litepcie
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c44a4b051f
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4ea7026747
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@ -282,7 +282,7 @@ class Memory(Special):
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data_regs = {}
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for port in memory.ports:
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if not port.async_read:
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if port.mode == WRITE_FIRST:
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if port.mode == WRITE_FIRST and port.we is not None:
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adr_reg = Signal(name_override="memadr")
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r += "reg [" + str(adrbits-1) + ":0] " \
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+ gn(adr_reg) + ";\n"
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@ -308,11 +308,11 @@ class Memory(Special):
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r += "\tif (" + gn(port.we) + ")\n"
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r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
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if not port.async_read:
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if port.mode == WRITE_FIRST:
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if port.mode == WRITE_FIRST and port.we is not None:
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rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
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else:
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bassign = gn(data_regs[id(port)]) + " <= " + gn(memory) + "[" + gn(port.adr) + "];\n"
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if port.mode == READ_FIRST:
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if port.mode == READ_FIRST or port.we is None:
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rd = "\t" + bassign
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elif port.mode == NO_CHANGE:
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rd = "\tif (!" + gn(port.we) + ")\n" \
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@ -328,7 +328,7 @@ class Memory(Special):
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if port.async_read:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(port.adr) + "];\n"
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else:
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if port.mode == WRITE_FIRST:
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if port.mode == WRITE_FIRST and port.we is not None:
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r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(adr_regs[id(port)]) + "];\n"
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else:
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r += "assign " + gn(port.dat_r) + " = " + gn(data_regs[id(port)]) + ";\n"
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