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gen/fhdl/specials: revert migen's commit d98502c6 (specials/Memory: homogenize read-only port syntax) since causing a regression with litepcie

This commit is contained in:
Florent Kermarrec 2017-06-10 21:53:53 +02:00
parent c44a4b051f
commit 4ea7026747
1 changed files with 4 additions and 4 deletions
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8
litex/gen/fhdl/specials.py
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@ -282,7 +282,7 @@ class Memory(Special):
data_regs = {} data_regs = {}
for port in memory.ports: for port in memory.ports:
if not port.async_read: if not port.async_read:
if port.mode == WRITE_FIRST: if port.mode == WRITE_FIRST and port.we is not None:
adr_reg = Signal(name_override="memadr") adr_reg = Signal(name_override="memadr")
r += "reg [" + str(adrbits-1) + ":0] " \ r += "reg [" + str(adrbits-1) + ":0] " \
+ gn(adr_reg) + ";\n" + gn(adr_reg) + ";\n"
@ -308,11 +308,11 @@ class Memory(Special):
r += "\tif (" + gn(port.we) + ")\n" r += "\tif (" + gn(port.we) + ")\n"
r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n" r += "\t\t" + gn(memory) + "[" + gn(port.adr) + "] <= " + gn(port.dat_w) + ";\n"
if not port.async_read: if not port.async_read:
if port.mode == WRITE_FIRST: if port.mode == WRITE_FIRST and port.we is not None:
rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n" rd = "\t" + gn(adr_regs[id(port)]) + " <= " + gn(port.adr) + ";\n"
else: else:
bassign = gn(data_regs[id(port)]) + " <= " + gn(memory) + "[" + gn(port.adr) + "];\n" bassign = gn(data_regs[id(port)]) + " <= " + gn(memory) + "[" + gn(port.adr) + "];\n"
if port.mode == READ_FIRST: if port.mode == READ_FIRST or port.we is None:
rd = "\t" + bassign rd = "\t" + bassign
elif port.mode == NO_CHANGE: elif port.mode == NO_CHANGE:
rd = "\tif (!" + gn(port.we) + ")\n" \ rd = "\tif (!" + gn(port.we) + ")\n" \
@ -328,7 +328,7 @@ class Memory(Special):
if port.async_read: if port.async_read:
r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(port.adr) + "];\n" r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(port.adr) + "];\n"
else: else:
if port.mode == WRITE_FIRST: if port.mode == WRITE_FIRST and port.we is not None:
r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(adr_regs[id(port)]) + "];\n" r += "assign " + gn(port.dat_r) + " = " + gn(memory) + "[" + gn(adr_regs[id(port)]) + "];\n"
else: else:
r += "assign " + gn(port.dat_r) + " = " + gn(data_regs[id(port)]) + ";\n" r += "assign " + gn(port.dat_r) + " = " + gn(data_regs[id(port)]) + ";\n"