software/liblitedram: simplify vtc/hardware/software controls.
- move vtc control to sdram_software_control_on/off. - remove sdram_calibration (duplicate of sdram_leveling). - be sure to call sdram_software_control_on/off before all litedram bios commands.
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e4555df095
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@ -25,13 +25,19 @@ define_command(sdram_init, sdram_init, "Initialize SDRAM (Init + Calibration)",
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#endif
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/**
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* Command "sdram_calibration"
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* Command "sdram_cal"
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*
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* Calibrate SDRAM
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*
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*/
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#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
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define_command(sdram_cal, sdram_calibration, "Calibrate SDRAM", LITEDRAM_CMDS);
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static void sdram_cal_handler(int nb_params, char **params)
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{
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sdram_software_control_on();
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sdram_leveling();
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sdram_software_control_off();
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}
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define_command(sdram_cal, sdram_cal_handler, "Calibrate SDRAM", LITEDRAM_CMDS);
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#endif
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#ifdef CSR_DDRPHY_CDLY_RST_ADDR
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@ -45,7 +51,9 @@ define_command(sdram_cal, sdram_calibration, "Calibrate SDRAM", LITEDRAM_CMDS);
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#if defined(CSR_SDRAM_BASE) && defined(CSR_DDRPHY_BASE)
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static void sdram_rst_cmd_delay_handler(int nb_params, char **params)
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{
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sdram_software_control_on();
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sdram_write_leveling_rst_cmd_delay(1);
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sdram_software_control_off();
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}
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define_command(sdram_rst_cmd_delay, sdram_rst_cmd_delay_handler, "Reset write leveling Cmd delay", LITEDRAM_CMDS);
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#endif
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@ -70,7 +78,9 @@ static void sdram_force_cmd_delay_handler(int nb_params, char **params)
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printf("Incorrect taps");
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return;
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}
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sdram_software_control_on();
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sdram_write_leveling_force_cmd_delay(taps, 1);
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sdram_software_control_off();
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}
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define_command(sdram_force_cmd_delay, sdram_force_cmd_delay_handler, "Force write leveling Cmd delay", LITEDRAM_CMDS);
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#endif
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@ -99,7 +109,9 @@ static void sdram_rst_dat_delay_handler(int nb_params, char **params)
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printf("Incorrect module");
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return;
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}
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sdram_software_control_on();
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sdram_write_leveling_rst_dat_delay(module, 1);
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sdram_software_control_off();
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}
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define_command(sdram_rst_dat_delay, sdram_rst_dat_delay_handler, "Reset write leveling Dat delay", LITEDRAM_CMDS);
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#endif
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@ -130,7 +142,9 @@ static void sdram_force_dat_delay_handler(int nb_params, char **params)
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printf("Incorrect taps");
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return;
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}
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sdram_software_control_on();
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sdram_write_leveling_force_dat_delay(module, taps, 1);
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sdram_software_control_off();
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}
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define_command(sdram_force_dat_delay, sdram_force_dat_delay_handler, "Reset write leveling Dat delay", LITEDRAM_CMDS);
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#endif
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@ -61,20 +61,31 @@ void sdram_software_control_on(void)
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{
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unsigned int previous;
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previous = sdram_dfii_control_read();
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/* Switch DFII to software control */
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if (previous != DFII_CONTROL_SOFTWARE) {
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sdram_dfii_control_write(DFII_CONTROL_SOFTWARE);
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printf("Switching SDRAM to software control.\n");
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}
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#if CSR_DDRPHY_EN_VTC_ADDR
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/* Disable Voltage/Temperature compensation */
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ddrphy_en_vtc_write(0);
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#endif
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}
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void sdram_software_control_off(void)
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{
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unsigned int previous;
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previous = sdram_dfii_control_read();
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/* Switch DFII to hardware control */
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if (previous != DFII_CONTROL_HARDWARE) {
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sdram_dfii_control_write(DFII_CONTROL_HARDWARE);
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printf("Switching SDRAM to hardware control.\n");
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}
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#if CSR_DDRPHY_EN_VTC_ADDR
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/* Enable Voltage/Temperature compensation */
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ddrphy_en_vtc_write(1);
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#endif
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}
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/*-----------------------------------------------------------------------*/
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@ -136,9 +147,6 @@ void sdram_write_leveling_rst_cmd_delay(int show) {
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void sdram_write_leveling_force_cmd_delay(int taps, int show) {
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_sdram_write_leveling_cmd_scan = 0;
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#if CSR_DDRPHY_EN_VTC_ADDR
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ddrphy_en_vtc_write(0);
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#endif
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if (show)
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printf("Forcing Cmd delay to %d taps\n", taps);
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ddrphy_cdly_rst_write(1);
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@ -147,9 +155,6 @@ void sdram_write_leveling_force_cmd_delay(int taps, int show) {
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cdelay(1000);
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taps--;
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}
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#if CSR_DDRPHY_EN_VTC_ADDR
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ddrphy_en_vtc_write(1);
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#endif
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}
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void sdram_write_leveling_rst_dat_delay(int module, int show) {
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@ -770,27 +775,6 @@ int sdram_leveling(void)
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}
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#endif
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/*-----------------------------------------------------------------------*/
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/* Calibration */
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/*-----------------------------------------------------------------------*/
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void sdram_calibration(void)
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{
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sdram_software_control_on();
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#ifdef CSR_DDRPHY_BASE
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#if CSR_DDRPHY_EN_VTC_ADDR
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ddrphy_en_vtc_write(0);
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#endif
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#if defined(SDRAM_PHY_WRITE_LEVELING_CAPABLE) || defined(SDRAM_PHY_READ_LEVELING_CAPABLE)
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sdram_leveling();
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#endif
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#if CSR_DDRPHY_EN_VTC_ADDR
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ddrphy_en_vtc_write(1);
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#endif
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#endif
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sdram_software_control_off();
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}
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/*-----------------------------------------------------------------------*/
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/* Initialization */
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/*-----------------------------------------------------------------------*/
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@ -816,7 +800,7 @@ int sdram_init(void)
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ddrctrl_init_error_write(0);
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#endif
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init_sequence();
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sdram_calibration();
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sdram_leveling();
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sdram_software_control_off();
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if(!memtest((unsigned int *) MAIN_RAM_BASE, MAIN_RAM_SIZE)) {
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#ifdef CSR_DDRCTRL_BASE
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@ -39,11 +39,6 @@ void sdram_read_leveling(void);
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/*-----------------------------------------------------------------------*/
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int sdram_leveling(void);
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/*-----------------------------------------------------------------------*/
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/* Calibration */
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/*-----------------------------------------------------------------------*/
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void sdram_calibration(void);
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/*-----------------------------------------------------------------------*/
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/* Initialization */
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/*-----------------------------------------------------------------------*/
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