cores/clock: Add initial GW1NSR's PLL support.
This commit is contained in:
Florent Kermarrec
parent
76c782c546
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4fe085cc1c
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Florent Kermarrec <florent@enjoy-digital.fr>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.cores.clock.common import *
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class Open(Signal): pass
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# GoWin / GW1NSRPLL --------------------------------------------------------------------------------
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class GW1NSRPLL(Module):
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nclkouts_max = 1
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pfd_freq_range = ( 3e6, 500e6)
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vco_freq_range = (400e6, 1000e6)
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def __init__(self, device, vco_margin=0):
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self.logger = logging.getLogger("GW1NPLL")
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self.logger.info("Creating GW1NPLL.".format())
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self.device = device
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self.vco_margin = vco_margin
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self.reset = Signal()
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self.locked = Signal()
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self.clkin_freq = None
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self.vcxo_freq = None
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self.nclkouts = 0
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self.clkouts = {}
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self.config = {}
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self.params = {}
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def register_clkin(self, clkin, freq):
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self.clkin = Signal()
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if isinstance(clkin, (Signal, ClockSignal)):
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self.comb += self.clkin.eq(clkin)
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else:
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raise ValueError
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self.clkin_freq = freq
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register_clkin_log(self.logger, clkin, freq)
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def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=True):
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assert self.nclkouts < self.nclkouts_max
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clkout = Signal()
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self.clkouts[self.nclkouts] = (clkout, freq, phase, margin)
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if with_reset:
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# FIXME: Should use PLL's lock but does not seem stable.
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self.specials += AsyncResetSynchronizer(cd, self.reset)
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self.comb += cd.clk.eq(clkout)
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create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
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self.nclkouts += 1
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def compute_config(self):
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config = {}
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for idiv in range(1, 64):
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config["idiv"] = idiv
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pfd_freq = self.clkin_freq/idiv
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pfd_freq_min, pfd_freq_max = self.pfd_freq_range
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if (pfd_freq < pfd_freq_min) or (pfd_freq > pfd_freq_max):
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continue
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for fdiv in range(1, 64):
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out_freq = self.clkin_freq*fdiv/idiv
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for odiv in [2, 4, 8, 16, 32, 48, 64, 80, 96, 112, 128]:
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config["odiv"] = odiv
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vco_freq = out_freq*odiv
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(vco_freq_min, vco_freq_max) = self.vco_freq_range
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if (vco_freq >= vco_freq_min*(1 + self.vco_margin) and
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vco_freq <= vco_freq_max*(1 - self.vco_margin)):
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for _n, (clk, f, p, _m) in sorted(self.clkouts.items()):
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if abs(out_freq - f) <= f*_m:
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config["clk{}_freq".format(_n)] = out_freq
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config["vco"] = vco_freq
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config["fdiv"] = fdiv
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compute_config_log(self.logger, config)
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return config
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raise ValueError("No PLL config found")
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def do_finalize(self):
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assert hasattr(self, "clkin")
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assert len(self.clkouts) == 1
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config = self.compute_config()
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# Based on UG286-1.3E Note.
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self.params.update(
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# Parameters.
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p_DEVICE = self.device, # FPGA Device.
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p_FCLKIN = str(self.clkin_freq/1e6), # Clk Input frequency (MHz).
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p_DYN_IDIV_SEL = "false", # Disable dynamic IDIV.
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p_IDIV_SEL = config["idiv"]-1, # Static IDIV value (1-64).
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p_DYN_FBDIV_SEL = "false", # Disable dynamic FBDIV.
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p_FBDIV_SEL = config["fdiv"]-1, # Static FBDIV value (1-64).
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p_DYN_ODIV_SEL = "false", # Disable dynamic ODIV.
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p_ODIV_SEL = config["odiv"], # Static ODIV value.
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p_PSDA_SEL = "0000", # -
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p_DYN_DA_EN = "false", # -
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p_DUTYDA_SEL = "1000", # -
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p_CLKOUT_FT_DIR = 1, # -
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p_CLKOUTP_FT_DIR = 1, # -
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p_CLKOUT_DLY_STEP = 0, # -
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p_CLKOUTP_DLY_STEP = 0, # -
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p_CLKFB_SEL = "internal", # Clk Feedback type (internal, external).
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p_CLKOUT_BYPASS = "false", # Clk Input to CLKOUT bypass.
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p_CLKOUTP_BYPASS = "false", # Clk Input to CLKOUTP bypass.
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p_CLKOUTD_BYPASS = "false", # Clk Input to CLKOUTD bypass.
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p_DYN_SDIV_SEL = 2, # Disable dynamic SDIV.
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p_CLKOUTD_SRC = "CLKOUT", # Recopy CLKOUT to CLKOUTD.
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p_CLKOUTD3_SRC = "CLKOUT", # Recopy CLKOUT to CLKOUTD3.
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# Inputs.
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i_CLKIN = self.clkin, # Clk Input.
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i_CLKFB = 0, # Clk Feedback.
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i_RESET = self.reset, # PLL Reset.
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i_RESET_P = 0, # PLL Power Down.
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i_ODSEL = 0, # Dynamic ODIV control.
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i_FBDSEL = 0, # Dynamic IDIV control.
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i_IDSEL = 0, # Dynamic FDIV control.
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i_PSDA = 0, # Dynamic phase control.
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i_DUTYDA = 0, # Dynamic duty cycle control.
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i_FDLY = 0, # Dynamic CLKOUTP delay control.
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i_VREN = 1,
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)
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clk0, f0, p0, m0 = self.clkouts[0]
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self.params.update(
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# Outputs.
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o_LOCK = self.locked, # PLL lock status.
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o_CLKOUT = clk0, # Clock output.
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o_CLKOUTP = Open(), # Clock output (With phase and duty cycle adjustement).
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o_CLKOUTD = Open(), # Clock divided from CLKOUT and CLKOUTP (controlled by SDIV).
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o_CLKOUTD3 = Open(), # Clock divided from CLKOUT and CLKOUTP (constant division of 3).
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)
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self.specials += Instance("PLLVR", **self.params)
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