cores: add External Memory Interface (EMIF) Wishbone bridge.
Useful to interface Processors/DSPs with LiteX. EMIF is generally used on Texas Instrument DSPs.
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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from migen import *
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from migen.genlib.cdc import MultiReg
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from litex.soc.interconnect import wishbone
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class EMIF(Module):
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"""External Memory Interface core
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Provides a simple EMIF to Wishbone Master bridge.
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"""
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def __init__(self, pads):
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self.bus = bus = wishbone.Interface()
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# # #
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# Resynchronization ------------------------------------------------------------------------
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cs_n = Signal(reset=1)
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oe_n = Signal(reset=1)
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we_n = Signal(reset=1)
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ba = Signal(2)
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addr = Signal(22)
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dqm_n = Signal(2)
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data = self.add_tristate(pads.data) if not hasattr(pads.data, "oe") else pads.data
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data_i = Signal(16)
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self.specials += [
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MultiReg(pads.cs_n, cs_n),
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MultiReg(pads.oe_n, oe_n),
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MultiReg(pads.we_n, we_n),
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MultiReg(pads.ba, ba),
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MultiReg(pads.addr, addr),
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MultiReg(data.i, data_i),
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]
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# EMIF <--> Wishbone -----------------------------------------------------------------------
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access = Signal()
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we_n_d = Signal()
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oe_n_d = Signal()
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self.sync += [
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we_n_d.eq(we_n),
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oe_n_d.eq(oe_n),
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If(~we_n & we_n_d,
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access.eq(1)
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).Elif(~oe_n & oe_n_d,
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access.eq(1)
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).Elif(bus.ack,
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access.eq(0)
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)
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]
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self.comb += [
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bus.stb.eq(~cs_n & access),
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bus.cyc.eq(~cs_n & access),
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bus.we.eq(~we_n),
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bus.adr.eq(addr),
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data.oe.eq(~oe_n),
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If(ba[1],
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bus.dat_w[:16].eq(data_i),
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bus.sel[:2].eq(~dqm_n)
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).Else(
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bus.dat_w[16:].eq(data_i),
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bus.sel[2:].eq(~dqm_n)
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)
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]
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self.sync += [
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If(bus.ack,
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If(ba[1],
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data.o.eq(bus.dat_r[:16])
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).Else(
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data.o.eq(bus.dat_r[16:])
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)
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)
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]
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def add_tristate(self, pad):
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t = TSTriple(len(pad))
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self.specials += t.get_tristate(pad)
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return t
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class EMIF16To32Adapter(Module):
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def __init__(self, emif):
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self.bus = bus = wishbone.Interface()
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# # #
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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If(emif.bus.stb & emif.bus.cyc,
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If(emif.bus.we,
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NextState("WRITE0")
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).Else(
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NextState("READ")
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)
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)
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)
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emif_bus_dat_w = Signal(32)
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fsm.act("WRITE0",
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emif.bus.ack.eq(1),
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If(emif.bus.sel[0],
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NextValue(emif_bus_dat_w[8*0:8*1], emif.bus.dat_w[8*0:8*1])
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),
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If(emif.bus.sel[1],
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NextValue(emif_bus_dat_w[8*1:8*2], emif.bus.dat_w[8*1:8*2])
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),
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If(emif.bus.sel[2],
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NextValue(emif_bus_dat_w[8*2:8*3], emif.bus.dat_w[8*2:8*3])
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),
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If(emif.bus.sel[3],
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NextValue(emif_bus_dat_w[8*3:8*4], emif.bus.dat_w[8*3:8*4])
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),
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NextState("WRITE1"),
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)
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fsm.act("WRITE1",
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bus.stb.eq(emif.bus.stb & emif.bus.cyc),
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bus.we.eq(1),
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bus.cyc.eq(emif.bus.stb & emif.bus.cyc),
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bus.adr.eq(emif.bus.adr),
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bus.sel.eq(0b1111),
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bus.dat_w.eq(emif_bus_dat_w),
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If(emif.bus.sel[0],
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bus.dat_w[8*0:8*1].eq(emif.bus.dat_w[8*0:8*1])
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),
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If(emif.bus.sel[1],
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bus.dat_w[8*1:8*2].eq(emif.bus.dat_w[8*1:8*2])
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),
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If(emif.bus.sel[2],
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bus.dat_w[8*2:8*3].eq(emif.bus.dat_w[8*2:8*3])
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),
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If(emif.bus.sel[3],
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bus.dat_w[8*3:8*4].eq(emif.bus.dat_w[8*3:8*4])
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),
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If(bus.stb & bus.ack,
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emif.bus.ack.eq(1),
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NextState("IDLE")
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)
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)
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fsm.act("READ",
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bus.stb.eq(1),
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bus.we.eq(0),
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bus.cyc.eq(1),
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bus.adr.eq(emif.bus.adr),
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If(bus.ack,
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emif.bus.ack.eq(1),
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emif.bus.dat_r.eq(bus.dat_r),
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NextState("IDLE")
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)
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)
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@ -0,0 +1,91 @@
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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import unittest
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from migen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.emif import EMIF
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class EMIFPads:
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def __init__(self):
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self.cs_n = Signal(reset=1)
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self.we_n = Signal(reset=1)
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self.oe_n = Signal(reset=1)
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self.wait_n = Signal(reset=1)
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self.ba = Signal(2)
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self.addr = Signal(22)
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self.dqm_n = Signal(2)
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self.data = Record([("oe", 1), ("o", 16), ("i", 16)])
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def emif_write(pads, addr, data, release_cs=True):
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for i in range(2):
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yield pads.cs_n.eq(0)
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yield pads.we_n.eq(1)
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yield pads.oe_n.eq(1)
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yield pads.ba.eq(1<<i)
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yield pads.addr.eq(addr)
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yield pads.data.i.eq((data >> 16*i) & 0xffff)
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yield
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yield pads.we_n.eq(0)
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for i in range(8):
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yield
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yield pads.we_n.eq(1)
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yield
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yield pads.cs_n.eq(release_cs)
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yield
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def emif_read(pads, addr, release_cs=True, release_oe=True):
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data = 0
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for i in range(2):
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yield pads.cs_n.eq(0)
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yield pads.we_n.eq(1)
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yield pads.oe_n.eq(release_oe)
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yield pads.ba.eq(1<<i)
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yield pads.addr.eq(addr)
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yield
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yield pads.oe_n.eq(0)
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for i in range(8):
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yield
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data >>= 16
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data |= (yield pads.data.o) << 16
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yield pads.oe_n.eq(release_oe)
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yield
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yield pads.cs_n.eq(release_cs)
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yield
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return data
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class TestEMIF(unittest.TestCase):
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def test_emif(self):
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pads = EMIFPads()
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def generator(dut):
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# Test writes/reads with cs release between accesses
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yield from emif_write(pads, 0, 0xdeadbeef, True)
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yield from emif_write(pads, 1, 0x12345678, True)
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yield from emif_write(pads, 2, 0x5aa55aa5, True)
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self.assertEqual((yield from emif_read(pads, 0, True)), 0xdeadbeef)
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self.assertEqual((yield from emif_read(pads, 1, True)), 0x12345678)
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self.assertEqual((yield from emif_read(pads, 2, True)), 0x5aa55aa5)
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# Test writes/reads without cs release between accesses
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yield from emif_write(pads, 0, 0xdeadbeef, False)
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yield from emif_write(pads, 1, 0x12345678, False)
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yield from emif_write(pads, 2, 0x5aa55aa5, False)
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self.assertEqual((yield from emif_read(pads, 0, False)), 0xdeadbeef)
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self.assertEqual((yield from emif_read(pads, 1, False)), 0x12345678)
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self.assertEqual((yield from emif_read(pads, 2, False)), 0x5aa55aa5)
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class DUT(Module):
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def __init__(self, pads):
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emif = EMIF(pads)
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self.submodules += emif
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mem = wishbone.SRAM(16, bus=emif.bus)
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self.submodules += mem
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dut = DUT(pads)
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run_simulation(dut, [generator(dut)])
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