boards: keep up to date with litex-boards, remove pcie_screamer target.

litex/boards/platforms/icebreaker.py

@@ -17,7 +17,7 @@ from litex.build.lattice.programmer import IceStormProgrammer
 
 _io = [
     # Clk / Rst
-    ("clk12", 0, Pins("35"), IOStandard("LVCMOS33"))
+    ("clk12", 0, Pins("35"), IOStandard("LVCMOS33")),
 
     # Leds
     ("user_led_n",    0, Pins("11"), IOStandard("LVCMOS33")),
@@ -89,8 +89,8 @@ class Platform(LatticePlatform):
     default_clk_name   = "clk12"
     default_clk_period = 1e9/12e6
 
-    def __init__(self):
+    def __init__(self, toolchain="icestorm"):
-        LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain="icestorm")
+        LatticePlatform.__init__(self, "ice40-up5k-sg48", _io, _connectors, toolchain=toolchain)
 
     def create_programmer(self):
         return IceStormProgrammer()

litex/boards/platforms/tinyfpga_bx.py

@@ -67,8 +67,8 @@ class Platform(LatticePlatform):
     default_clk_name   = "clk16"
     default_clk_period = 1e9/16e6
 
-    def __init__(self):
+    def __init__(self, toolchain="icestorm"):
-        LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, toolchain="icestorm")
+        LatticePlatform.__init__(self, "ice40-lp8k-cm81", _io, _connectors, toolchain=toolchain)
         self.add_extension(serial)
 
     def create_programmer(self):

litex/boards/platforms/ulx3s.py

@@ -146,11 +146,11 @@ class Platform(LatticePlatform):
     default_clk_name   = "clk25"
     default_clk_period = 1e9/25e6
 
-    def __init__(self, device="LFE5U-45F", revision="2.0", **kwargs):
+    def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis", **kwargs):
         assert device in ["LFE5U-12F", "LFE5U-25F", "LFE5U-45F", "LFE5U-85F"]
         assert revision in ["1.7", "2.0"]
         _io = _io_common + {"1.7": _io_1_7, "2.0": _io_2_0}[revision]
-        LatticePlatform.__init__(self, device + "-6BG381C", _io, **kwargs)
+        LatticePlatform.__init__(self, device + "-6BG381C", _io, toolchain=toolchain, **kwargs)
 
     def create_programmer(self):
         return UJProg()

litex/boards/platforms/versa_ecp5.py

@@ -235,9 +235,9 @@ class Platform(LatticePlatform):
     default_clk_name   = "clk100"
     default_clk_period = 1e9/100e6
 
-    def __init__(self, device="LFE5UM5G", **kwargs):
+    def __init__(self, device="LFE5UM5G", toolchain="trellis", **kwargs):
         assert device in ["LFE5UM5G", "LFE5UM"]
-        LatticePlatform.__init__(self, device + "-45F-8BG381C", _io, _connectors, **kwargs)
+        LatticePlatform.__init__(self, device + "-45F-8BG381C", _io, _connectors, toolchain=toolchain, **kwargs)
 
     def create_programmer(self):
         return OpenOCDJTAGProgrammer("openocd_versa_ecp5.cfg")

litex/boards/targets/arty.py

@@ -125,19 +125,25 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
     parser.add_argument("--build", action="store_true",     help="Build bitstream")
     parser.add_argument("--load",  action="store_true",     help="Load bitstream")
-    parser.add_argument("--toolchain", default="vivado", help="Gateware toolchain to use, vivado (default) or symbiflow")
+    parser.add_argument("--toolchain", default="vivado",    help="FPGA toolchain: vivado (default) or symbiflow")
-    builder_args(parser)
+    parser.add_argument("--sys-clk-freq",    default=100e6, help="System clock frequency (default: 100MHz)")
-    soc_sdram_args(parser)
-    vivado_build_args(parser)
     parser.add_argument("--with-ethernet",   action="store_true", help="Enable Ethernet support")
     parser.add_argument("--with-etherbone",  action="store_true", help="Enable Etherbone support")
     parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
     parser.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support")
+    builder_args(parser)
+    soc_sdram_args(parser)
+    vivado_build_args(parser)
     args = parser.parse_args()
 
     assert not (args.with_ethernet and args.with_etherbone)
-    soc = BaseSoC(args.toolchain, with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone,
+    soc = BaseSoC(
-        **soc_sdram_argdict(args))
+	    toolchain      = args.toolchain,
+        sys_clk_freq   = int(float(args.sys_clk_freq)),
+        with_ethernet  = args.with_ethernet,
+        with_etherbone = args.with_etherbone,
+        **soc_sdram_argdict(args)
+    )
     assert not (args.with_spi_sdcard and args.with_sdcard)
     soc.platform.add_extension(arty._sdcard_pmod_io)
     if args.with_spi_sdcard:

litex/boards/targets/de0nano.py

@@ -98,12 +98,17 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on DE0-Nano")
     parser.add_argument("--build",        action="store_true", help="Build bitstream")
     parser.add_argument("--load",         action="store_true", help="Load bitstream")
-    parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
+    parser.add_argument("--sys-clk-freq", default=50e6,        help="System clock frequency (default: 50MHz)")
+    parser.add_argument("--sdram-rate",   default="1:1",       help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args))
+    soc = BaseSoC(
+        sys_clk_freq = int(float(args.sys_clk_freq)),
+        sdram_rate   = args.sdram_rate,
+        **soc_sdram_argdict(args)
+    )
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 

litex/boards/targets/genesys2.py

@@ -47,7 +47,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, with_etherbone=False, **kwargs):
         platform = genesys2.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -99,15 +99,20 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Genesys2")
     parser.add_argument("--build",          action="store_true", help="Build bitstream")
     parser.add_argument("--load",           action="store_true", help="Load bitstream")
+    parser.add_argument("--sys-clk-freq",   default=100e6,       help="System clock frequency (default: 100MHz)")
+    parser.add_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet",  action="store_true", help="enable Ethernet support")
-    parser.add_argument("--with-etherbone", action="store_true", help="enable Etherbone support")
     args = parser.parse_args()
 
     assert not (args.with_ethernet and args.with_etherbone)
-    soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone,
+    soc = BaseSoC(
-        **soc_sdram_argdict(args))
+        sys_clk_freq   = int(float(args.sys_clk_freq)),
+        with_ethernet  = args.with_ethernet,
+        with_etherbone = args.with_etherbone,
+        **soc_sdram_argdict(args)
+    )
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 

litex/boards/targets/icebreaker.py

@@ -69,8 +69,7 @@ class _CRG(Module):
 
 class BaseSoC(SoCCore):
     mem_map = {**SoCCore.mem_map, **{"spiflash": 0x80000000}}
-    def __init__(self, bios_flash_offset, **kwargs):
+    def __init__(self, bios_flash_offset, sys_clk_freq=int(24e6), **kwargs):
-        sys_clk_freq = int(24e6)
         platform = icebreaker.Platform()
         platform.add_extension(icebreaker.break_off_pmod)
 
@@ -125,13 +124,18 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
     parser.add_argument("--build",             action="store_true", help="Build bitstream")
     parser.add_argument("--load",              action="store_true", help="Load bitstream")
-    parser.add_argument("--bios-flash-offset", default=0x40000,     help="BIOS offset in SPI Flash")
     parser.add_argument("--flash",             action="store_true", help="Flash Bitstream")
+    parser.add_argument("--sys-clk-freq",      default=24e6,        help="System clock frequency (default: 24MHz)")
+    parser.add_argument("--bios-flash-offset", default=0x40000,     help="BIOS offset in SPI Flash (default: 0x40000)")
     builder_args(parser)
     soc_core_args(parser)
     args = parser.parse_args()
 
-    soc     = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args))
+    soc = BaseSoC(
+        bios_flash_offset = args.bios_flash_offset,
+        sys_clk_freq      = int(float(args.sys_clk_freq)),
+        **soc_core_argdict(args)
+    )
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 

litex/boards/targets/kc705.py

@@ -26,6 +26,9 @@ from litedram.phy import s7ddrphy
 
 from liteeth.phy import LiteEthPHY
 
+from litepcie.phy.s7pciephy import S7PCIEPHY
+from litepcie.software import generate_litepcie_software
+
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -49,7 +52,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_sata=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_pcie=False, with_sata=False, **kwargs):
         platform = kc705.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -87,6 +90,14 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
+        # PCIe -------------------------------------------------------------------------------------
+        if with_pcie:
+            self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
+                data_width = 128,
+                bar0_size  = 0x20000)
+            self.add_csr("pcie_phy")
+            self.add_pcie(phy=self.pcie_phy, ndmas=1)
+
         # SATA -------------------------------------------------------------------------------------
         if with_sata:
             from litex.build.generic_platform import Subsignal, Pins
@@ -134,16 +145,28 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on KC705")
     parser.add_argument("--build",         action="store_true", help="Build bitstream")
     parser.add_argument("--load",          action="store_true", help="Load bitstream")
+    parser.add_argument("--sys-clk-freq",  default=125e6,       help="System clock frequency (default: 125MHz)")
+    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--with-pcie",     action="store_true", help="Enable PCIe support")
+    parser.add_argument("--driver",        action="store_true", help="Generate PCIe driver")
+    parser.add_argument("--with-sata",     action="store_true", help="Enable SATA support (over SFP2SATA)")
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
-    parser.add_argument("--with-sata",     action="store_true", help="Enable SATA support (over SFP2SATA)")
     args = parser.parse_args()
 
-    soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args))
+    soc = BaseSoC(
+        sys_clk_freq  = int(float(args.sys_clk_freq)),
+        with_ethernet = args.with_ethernet,
+        with_pcie     = args.with_pcie,
+        with_sata     = args.with_sata,
+        **soc_sdram_argdict(args)
+    )
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 
+    if args.driver:
+        generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
+
     if args.load:
         prog = soc.platform.create_programmer()
         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))

litex/boards/targets/kcu105.py

@@ -25,6 +25,9 @@ from litedram.phy import usddrphy
 
 from liteeth.phy.ku_1000basex import KU_1000BASEX
 
+from litepcie.phy.uspciephy import USPCIEPHY
+from litepcie.software import generate_litepcie_software
+
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -59,7 +62,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(125e6), with_ethernet=False, with_etherbone=False, with_pcie=False, **kwargs):
         platform = kcu105.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -101,6 +104,14 @@ class BaseSoC(SoCCore):
             if with_etherbone:
                 self.add_etherbone(phy=self.ethphy)
 
+        # PCIe -------------------------------------------------------------------------------------
+        if with_pcie:
+            self.submodules.pcie_phy = USPCIEPHY(platform, platform.request("pcie_x4"),
+                data_width = 128,
+                bar0_size  = 0x20000)
+            self.add_csr("pcie_phy")
+            self.add_pcie(phy=self.pcie_phy, ndmas=1)
+
         # Leds -------------------------------------------------------------------------------------
         self.submodules.leds = LedChaser(
             pads         = platform.request_all("user_led"),
@@ -113,18 +124,29 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on KCU105")
     parser.add_argument("--build",          action="store_true", help="Build bitstream")
     parser.add_argument("--load",           action="store_true", help="Load bitstream")
-    builder_args(parser)
+    parser.add_argument("--sys-clk-freq",   default=125e6,       help="System clock frequency (default: 125MHz)")
-    soc_sdram_args(parser)
     parser.add_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support")
     parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
+    parser.add_argument("--with-pcie",      action="store_true", help="Enable PCIe support")
+    parser.add_argument("--driver",         action="store_true", help="Generate PCIe driver")
+    builder_args(parser)
+    soc_sdram_args(parser)
     args = parser.parse_args()
 
     assert not (args.with_ethernet and args.with_etherbone)
-    soc = BaseSoC(with_ethernet=args.with_ethernet, with_etherbone=args.with_etherbone,
+    soc = BaseSoC(
-        **soc_sdram_argdict(args))
+        sys_clk_freq   = int(float(args.sys_clk_freq)),
+        with_ethernet  = args.with_ethernet,
+        with_etherbone = args.with_etherbone,
+        with_pcie      = args.with_pcie,
+        **soc_sdram_argdict(args)
+	)
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 
+    if args.driver:
+        generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
+
     if args.load:
         prog = soc.platform.create_programmer()
         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))

litex/boards/targets/minispartan6.py

@@ -101,12 +101,17 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on MiniSpartan6")
     parser.add_argument("--build",        action="store_true", help="Build bitstream")
     parser.add_argument("--load",         action="store_true", help="Load bitstream")
-    parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
+    parser.add_argument("--sys-clk-freq", default=80e6,        help="System clock frequency (default: 80MHz)")
+    parser.add_argument("--sdram-rate",   default="1:1",       help="SDRAM Rate: 1:1 Full Rate (default) or 1:2 Half Rate")
     builder_args(parser)
     soc_sdram_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(sdram_rate=args.sdram_rate, **soc_sdram_argdict(args))
+    soc = BaseSoC(
+        sys_clk_freq = int(float(args.sys_clk_freq)),
+        sdram_rate   = args.sdram_rate,
+        **soc_sdram_argdict(args)
+    )
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 

litex/boards/targets/netv2.py

@@ -8,15 +8,18 @@
 
 import os
 import argparse
+import sys
 
 from migen import *
 
-from litex.boards.platforms import netv2
+from litex_boards.platforms import netv2
 
-from litex.soc.cores.clock import *
+from litex.soc.interconnect.csr import *
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.soc_sdram import *
 from litex.soc.integration.builder import *
+
+from litex.soc.cores.clock import *
 from litex.soc.cores.led import LedChaser
 
 from litedram.modules import K4B2G1646F
@@ -24,6 +27,9 @@ from litedram.phy import s7ddrphy
 
 from liteeth.phy.rmii import LiteEthPHYRMII
 
+from litepcie.phy.s7pciephy import S7PCIEPHY
+from litepcie.software import generate_litepcie_software
+
 # CRG ----------------------------------------------------------------------------------------------
 
 class _CRG(Module):
@@ -36,11 +42,13 @@ class _CRG(Module):
         self.clock_domains.cd_clk100    = ClockDomain()
         self.clock_domains.cd_eth       = ClockDomain()
 
-        # # #
+        # Clk/Rst
+        clk50 = platform.request("clk50")
 
+        # PLL
         self.submodules.pll = pll = S7PLL(speedgrade=-1)
         self.comb += pll.reset.eq(self.rst)
-        pll.register_clkin(platform.request("clk50"), 50e6)
+        pll.register_clkin(clk50, 50e6)
         pll.create_clkout(self.cd_sys,       sys_clk_freq)
         pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
         pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
@@ -53,7 +61,7 @@ class _CRG(Module):
 # BaseSoC ------------------------------------------------------------------------------------------
 
 class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), with_ethernet=False, **kwargs):
+    def __init__(self, sys_clk_freq=int(100e6), with_pcie=False, with_ethernet=False, **kwargs):
         platform = netv2.Platform()
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -90,6 +98,14 @@ class BaseSoC(SoCCore):
             self.add_csr("ethphy")
             self.add_ethernet(phy=self.ethphy)
 
+        # PCIe -------------------------------------------------------------------------------------
+        if with_pcie:
+            self.submodules.pcie_phy = S7PCIEPHY(platform, platform.request("pcie_x4"),
+                data_width = 128,
+                bar0_size  = 0x20000)
+            self.add_csr("pcie_phy")
+            self.add_pcie(phy=self.pcie_phy, ndmas=1)
+
         # Leds -------------------------------------------------------------------------------------
         self.submodules.leds = LedChaser(
             pads         = platform.request_all("user_led"),
@@ -102,15 +118,34 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on NeTV2")
     parser.add_argument("--build",           action="store_true", help="Build bitstream")
     parser.add_argument("--load",            action="store_true", help="Load bitstream")
+    parser.add_argument("--sys-clk-freq",    default=100e6,       help="System clock frequency (default: 100MHz)")
+    parser.add_argument("--with-ethernet",   action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--with-pcie",       action="store_true", help="Enable PCIe support")
+    parser.add_argument("--driver",          action="store_true", help="Generate PCIe driver")
+    parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
+    parser.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support")
+
     builder_args(parser)
     soc_sdram_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
     args = parser.parse_args()
 
-    soc = BaseSoC(with_ethernet=args.with_ethernet, **soc_sdram_argdict(args))
+    soc = BaseSoC(
+        sys_clk_freq  = int(float(args.sys_clk_freq)),
+        with_ethernet = args.with_ethernet,
+        with_pcie     = args.with_pcie,
+        **soc_sdram_argdict(args)
+    )
+    assert not (args.with_spi_sdcard and args.with_sdcard)
+    if args.with_spi_sdcard:
+        soc.add_spi_sdcard()
+    if args.with_sdcard:
+        soc.add_sdcard()
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 
+    if args.driver:
+        generate_litepcie_software(soc, os.path.join(builder.output_dir, "driver"))
+
     if args.load:
         prog = soc.platform.create_programmer()
         prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))

litex/boards/targets/nexys4ddr.py

@@ -100,17 +100,19 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Nexys4DDR")
     parser.add_argument("--build",           action="store_true", help="Build bitstream")
     parser.add_argument("--load",            action="store_true", help="Load bitstream")
-    builder_args(parser)
+    parser.add_argument("--sys-clk-freq",    default=75e6,        help="System clock frequency (default: 75MHz)")
-    soc_sdram_args(parser)
-    parser.add_argument("--sys-clk-freq",  default=75e6,          help="System clock frequency (default=75MHz)")
     parser.add_argument("--with-ethernet",   action="store_true", help="Enable Ethernet support")
     parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
     parser.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support")
+    builder_args(parser)
+    soc_sdram_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
+    soc = BaseSoC(
+        sys_clk_freq  = int(float(args.sys_clk_freq)),
         with_ethernet = args.with_ethernet,
-        **soc_sdram_argdict(args))
+        **soc_sdram_argdict(args)
+    )
     assert not (args.with_spi_sdcard and args.with_sdcard)
     if args.with_spi_sdcard:
         soc.add_spi_sdcard()

litex/boards/targets/nexys_video.py

@@ -130,15 +130,21 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Nexys Video")
     parser.add_argument("--build",           action="store_true", help="Build bitstream")
     parser.add_argument("--load",            action="store_true", help="Load bitstream")
-    builder_args(parser)
+    parser.add_argument("--sys-clk-freq",    default=100e6,       help="System clock frequency (default: 100MHz)")
-    soc_sdram_args(parser)
     parser.add_argument("--with-ethernet",   action="store_true", help="Enable Ethernet support")
     parser.add_argument("--with-spi-sdcard", action="store_true", help="Enable SPI-mode SDCard support")
     parser.add_argument("--with-sdcard",     action="store_true", help="Enable SDCard support")
     parser.add_argument("--with-sata",       action="store_true", help="Enable SATA support (over FMCRAID)")
+    builder_args(parser)
+    soc_sdram_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(with_ethernet=args.with_ethernet, with_sata=args.with_sata, **soc_sdram_argdict(args))
+    soc = BaseSoC(
+        sys_clk_freq  = int(float(args.sys_clk_freq)),
+        with_ethernet = args.with_ethernet,
+        with_sata     = args.with_sata,
+        **soc_sdram_argdict(args)
+    )
     assert not (args.with_spi_sdcard and args.with_sdcard)
     if args.with_spi_sdcard:
         soc.add_spi_sdcard()

litex/boards/targets/pcie_screamer.py

@@ -1,87 +0,0 @@
-#!/usr/bin/env python3
-
-#
-# This file is part of LiteX.
-#
-# Copyright (c) 2016-2019 Florent Kermarrec <florent@enjoy-digital.fr>
-# SPDX-License-Identifier: BSD-2-Clause
-
-import argparse
-
-from migen import *
-
-from litex.boards.platforms import pcie_screamer
-from litex.build.xilinx.vivado import vivado_build_args, vivado_build_argdict
-
-from litex.soc.cores.clock import *
-from litex.soc.integration.soc_core import *
-from litex.soc.integration.soc_sdram import *
-from litex.soc.integration.builder import *
-
-from litedram.modules import MT41K128M16
-from litedram.phy import s7ddrphy
-
-# CRG ----------------------------------------------------------------------------------------------
-
-class _CRG(Module):
-    def __init__(self, platform, sys_clk_freq):
-        self.clock_domains.cd_sys       = ClockDomain()
-        self.clock_domains.cd_sys4x     = ClockDomain(reset_less=True)
-        self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True)
-        self.clock_domains.cd_clk200    = ClockDomain()
-        # # #
-
-        self.submodules.pll = pll = S7PLL(speedgrade=-1)
-        pll.register_clkin(platform.request("clk100"), 100e6)
-        pll.create_clkout(self.cd_sys,       sys_clk_freq)
-        pll.create_clkout(self.cd_sys4x,     4*sys_clk_freq)
-        pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90)
-        pll.create_clkout(self.cd_clk200,    200e6)
-
-        self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200)
-
-# BaseSoC ------------------------------------------------------------------------------------------
-
-class BaseSoC(SoCCore):
-    def __init__(self, sys_clk_freq=int(100e6), **kwargs):
-        platform = pcie_screamer.Platform()
-
-        # SoCCore ----------------------------------------------------------------------------------
-        SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
-
-        # CRG --------------------------------------------------------------------------------------
-        self.submodules.crg = _CRG(platform, sys_clk_freq)
-
-        # DDR3 SDRAM -------------------------------------------------------------------------------
-        if not self.integrated_main_ram_size:
-            self.submodules.ddrphy = s7ddrphy.A7DDRPHY(platform.request("ddram"),
-                memtype      = "DDR3",
-                nphases      = 4,
-                sys_clk_freq = sys_clk_freq)
-            self.add_csr("ddrphy")
-            self.add_sdram("sdram",
-                phy                     = self.ddrphy,
-                module                  = MT41K128M16(sys_clk_freq, "1:4"),
-                origin                  = self.mem_map["main_ram"],
-                size                    = kwargs.get("max_sdram_size", 0x40000000),
-                l2_cache_size           = kwargs.get("l2_size", 8192),
-                l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
-                l2_cache_reverse        = True
-            )
-
-# Build --------------------------------------------------------------------------------------------
-
-def main():
-    parser = argparse.ArgumentParser(description="LiteX SoC on PCIe Screamer")
-    builder_args(parser)
-    soc_sdram_args(parser)
-    vivado_build_args(parser)
-    args = parser.parse_args()
-
-    soc = BaseSoC(**soc_sdram_argdict(args))
-    builder = Builder(soc, **builder_argdict(args))
-    builder.build(**vivado_build_argdict(args))
-
-
-if __name__ == "__main__":
-    main()

litex/boards/targets/simple.py

@@ -3,7 +3,7 @@
 #
 # This file is part of LiteX.
 #
-# Copyright (c) 2014-2019 Florent Kermarrec <florent@enjoy-digital.fr>
+# Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
 # Copyright (c) 2013-2014 Sebastien Bourdeauducq <sb@m-labs.hk>
 # SPDX-License-Identifier: BSD-2-Clause
 
@@ -18,7 +18,7 @@ from litex.build.io import CRG
 from litex.soc.integration.soc_core import *
 from litex.soc.integration.builder import *
 
-from liteeth.phy import LiteEthPHY
+from litex.soc.cores.led import LedChaser
 
 # BaseSoC ------------------------------------------------------------------------------------------
 
@@ -35,36 +35,39 @@ class BaseSoC(SoCCore):
         # CRG --------------------------------------------------------------------------------------
         self.submodules.crg = CRG(platform.request(platform.default_clk_name))
 
-        # Ethernet ---------------------------------------------------------------------------------
+        # Leds -------------------------------------------------------------------------------------
-        if with_ethernet:
+        try:
-            self.submodules.ethphy = LiteEthPHY(
+            self.submodules.leds = LedChaser(
-                clock_pads = self.platform.request("eth_clocks"),
+                pads         = platform.request_all("user_led"),
-                pads       = self.platform.request("eth"),
+                sys_clk_freq = sys_clk_freq)
-                clk_freq   = self.clk_freq)
+            self.add_csr("leds")
-            self.add_csr("ethphy")
+        except:
-            self.add_ethernet(phy=self.ethphy)
+            pass
 
 # Build --------------------------------------------------------------------------------------------
 
 def main():
     parser = argparse.ArgumentParser(description="Generic LiteX SoC")
+    parser.add_argument("platform",                             help="Module name of the platform to build for")
     parser.add_argument("--build",         action="store_true", help="Build bitstream")
+    parser.add_argument("--load",          action="store_true", help="Load bitstream")
+    parser.add_argument("--toolchain",     default=None,        help="FPGA toolchain (None default)")
     builder_args(parser)
     soc_core_args(parser)
-    parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support")
-    parser.add_argument("platform",                             help="Module name of the platform to build for")
-    parser.add_argument("--toolchain", default=None,   help="FPGA gateware toolchain used for build")
     args = parser.parse_args()
 
     platform_module = importlib.import_module(args.platform)
+    platform_kwargs = {}
     if args.toolchain is not None:
-        platform = platform_module.Platform(toolchain=args.toolchain)
+        platform_kwargs["toolchain"] = args.toolchain
-    else:
+    platform = platform_module.Platform(**platform_kwargs)
-        platform = platform_module.Platform()
+    soc = BaseSoC(platform,**soc_core_argdict(args))
-    soc = BaseSoC(platform, with_ethernet=args.with_ethernet, **soc_core_argdict(args))
     builder = Builder(soc, **builder_argdict(args))
     builder.build(run=args.build)
 
+    if args.load:
+        prog = soc.platform.create_programmer()
+        prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + platform.bitstream_ext))
 
 if __name__ == "__main__":
     main()

litex/boards/targets/ulx3s.py

@@ -82,7 +82,6 @@ class _CRG(Module):
 class BaseSoC(SoCCore):
     def __init__(self, device="LFE5U-45F", revision="2.0", toolchain="trellis",
         sys_clk_freq=int(50e6), sdram_module_cls="MT48LC16M16", sdram_rate="1:1", **kwargs):
-
         platform = ulx3s.Platform(device=device, revision=revision, toolchain=toolchain)
 
         # SoCCore ----------------------------------------------------------------------------------
@@ -131,21 +130,24 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on ULX3S")
     parser.add_argument("--build",           action="store_true",   help="Build bitstream")
     parser.add_argument("--load",            action="store_true",   help="Load bitstream")
-    parser.add_argument("--toolchain", default="trellis",   help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--toolchain",       default="trellis",     help="FPGA toolchain: trellis (default) or diamond")
-    parser.add_argument("--device",             dest="device",    default="LFE5U-45F", help="FPGA device, ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F")
+    parser.add_argument("--device",          default="LFE5U-45F",   help="FPGA device: LFE5U-12F, LFE5U-25F, LFE5U-45F (default)  or LFE5U-85F")
-    parser.add_argument("--revision", default="2.0", type=str,  help="Board revision 2.0 (default), 1.7")
+    parser.add_argument("--revision",        default="2.0",         help="Board revision: 2.0 (default) or 1.7")
-    parser.add_argument("--sys-clk-freq", default=50e6,           help="System clock frequency (default=50MHz)")
+    parser.add_argument("--sys-clk-freq",    default=50e6,          help="System clock frequency  (default: 50MHz)")
-    parser.add_argument("--sdram-module", default="MT48LC16M16",  help="SDRAM module: MT48LC16M16, AS4C32M16 or AS4C16M16 (default=MT48LC16M16)")
+    parser.add_argument("--sdram-module",    default="MT48LC16M16", help="SDRAM module: MT48LC16M16 (default), AS4C32M16 or AS4C16M16")
     parser.add_argument("--with-spi-sdcard", action="store_true",   help="Enable SPI-mode SDCard support")
     parser.add_argument("--with-sdcard",     action="store_true",   help="Enable SDCard support")
     parser.add_argument("--with-oled",       action="store_true",   help="Enable SDD1331 OLED support")
-    parser.add_argument("--sdram-rate",  default="1:1", help="SDRAM Rate 1:1 Full Rate (default), 1:2 Half Rate")
+    parser.add_argument("--sdram-rate",      default="1:1",         help="SDRAM Rate: 1:1 Full Rate (default), 1:2 Half Rate")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)
     args = parser.parse_args()
 
-    soc = BaseSoC(device=args.device, revision=args.revision, toolchain=args.toolchain,
+    soc = BaseSoC(
+        device           = args.device,
+        revision         = args.revision,
+        toolchain        = args.toolchain,
         sys_clk_freq     = int(float(args.sys_clk_freq)),
         sdram_module_cls = args.sdram_module,
         sdram_rate       = args.sdram_rate,

litex/boards/targets/versa_ecp5.py

@@ -136,25 +136,27 @@ def main():
     parser = argparse.ArgumentParser(description="LiteX SoC on Versa ECP5")
     parser.add_argument("--build",          action="store_true", help="Build bitstream")
     parser.add_argument("--load",           action="store_true", help="Load bitstream")
-    parser.add_argument("--toolchain", default="trellis", help="Gateware toolchain to use, trellis (default) or diamond")
+    parser.add_argument("--toolchain",      default="trellis",   help="FPGA toolchain: trellis (default) or diamond")
+    parser.add_argument("--sys-clk-freq",   default=75e6,        help="System clock frequency (default: 75MHz)")
+    parser.add_argument("--device",         default="LFE5UM5G",  help="FPGA device (LFE5UM5G (default) or LFE5UM)")
+    parser.add_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support")
+    parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
+    parser.add_argument("--eth-phy",        default=0, type=int, help="Ethernet PHY: 0 (default) or 1")
     builder_args(parser)
     soc_sdram_args(parser)
     trellis_args(parser)
-    parser.add_argument("--sys-clk-freq",   default=75e6,        help="System clock frequency (default=75MHz)")
-    parser.add_argument("--device",         default="LFE5UM5G",  help="ECP5 device (LFE5UM5G (default) or LFE5UM)")
-    parser.add_argument("--with-ethernet",  action="store_true", help="Enable Ethernet support")
-    parser.add_argument("--with-etherbone", action="store_true", help="Enable Etherbone support")
-    parser.add_argument("--eth-phy",        default=0, type=int, help="Ethernet PHY 0 or 1 (default=0)")
     args = parser.parse_args()
 
     assert not (args.with_ethernet and args.with_etherbone)
-    soc = BaseSoC(sys_clk_freq=int(float(args.sys_clk_freq)),
+    soc = BaseSoC(
+        sys_clk_freq   = int(float(args.sys_clk_freq)),
         device         = args.device,
         with_ethernet  = args.with_ethernet,
         with_etherbone = args.with_etherbone,
         eth_phy        = args.eth_phy,
         toolchain      = args.toolchain,
-        **soc_sdram_argdict(args))
+        **soc_sdram_argdict(args)
+    )
     builder = Builder(soc, **builder_argdict(args))
     builder_kargs = trellis_argdict(args) if args.toolchain == "trellis" else {}
     builder.build(**builder_kargs, run=args.build)