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interconnect/csr_bus: Add missing part of the previous fix...

This commit is contained in:
Florent Kermarrec 2022-10-21 23:06:25 +02:00
parent 76d3a77cf3
commit 50acdf73a4
1 changed files with 8 additions and 2 deletions
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10
litex/soc/interconnect/csr_bus.py
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@ -225,9 +225,11 @@ class CSRBankArray(Module):
# Collect CSR Registers.
# ---------------------
csrs = []
if hasattr(obj, "get_csrs"):
if hasattr(obj, "get_csrs"): # FIXME: Simplify.
if "sort" in obj.get_csrs.__code__.co_varnames:
csrs = obj.get_csrs(sort=True)
else:
csrs = obj.get_csrs()
# Collect CSR Memories.
# ---------------------
@ -252,10 +254,14 @@ class CSRBankArray(Module):
# Collect CSR Constants.
# ----------------------
if hasattr(obj, "get_constants"):
if hasattr(obj, "get_constants"): # FIXME: Simplify.
if "sort" in obj.get_constants.__code__.co_varnames:
for constant in obj.get_constants(sort=True):
self.constants.append((name, constant))
else:
for constant in obj.get_constants():
self.constants.append((name, constant))
# Create CSRBank with CSRs found.
# -------------------------------