Merge pull request #551 from antmicro/mglb/symbiflow-toolchain-xilinx-7-support
Add Symbiflow toolchain support for Xilinx 7-series
This commit is contained in:
enjoy-digital
GitHub
commit
5104d07a13
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@ -0,0 +1,35 @@
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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from litex.build.generic_platform import *
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from litex.build.xilinx import XilinxPlatform
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from litex.build.openocd import OpenOCD
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from litex.boards.platforms.arty import _io, _connectors
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# Platform -----------------------------------------------------------------------------------------
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class Platform(XilinxPlatform):
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default_clk_name = "clk100"
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default_clk_period = 1e9/100e6
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def __init__(self, variant="a7-35"):
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device = {
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"a7-35": {"part": "xc7a35tcsg324-1", "symbiflow-device": "xc7a50t_test"},
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}[variant]
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XilinxPlatform.__init__(self, device["part"], _io, _connectors, toolchain="symbiflow")
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self.toolchain.symbiflow_device = device["symbiflow-device"]
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def create_programmer(self):
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bscan_spi = "bscan_spi_xc7a100t.bit" if "xc7a100t" in self.device else "bscan_spi_xc7a35t.bit"
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return OpenOCD("openocd_xc7_ft2232.cfg", bscan_spi)
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def do_finalize(self, fragment):
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# Prevent GenericPlatform from creating period constraint on input clock
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pass
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def add_period_constraint(self, clk, period, phase=0):
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if clk is None: return
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if hasattr(clk, "p"):
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clk = clk.p
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self.toolchain.add_period_constraint(self, clk, period, phase)
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@ -0,0 +1,78 @@
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#!/usr/bin/env python3
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# This file is Copyright (c) 2015-2019 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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import os
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import argparse
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from migen import *
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from litex.boards.platforms import arty_symbiflow
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from litex.build.xilinx.symbiflow import symbiflow_build_args, symbiflow_build_argdict
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from litex.soc.cores.clock import *
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litex.soc.cores.led import LedChaser
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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clk100_ibuf = Signal()
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clk100_buf = Signal()
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self.specials += Instance("IBUF", i_I=platform.request("clk100"), o_O=clk100_ibuf)
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self.specials += Instance("BUFG", i_I=clk100_ibuf, o_O=clk100_buf)
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self.submodules.pll = pll = S7PLL(speedgrade=-1)
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self.comb += pll.reset.eq(~platform.request("cpu_reset"))
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pll.register_clkin(clk100_buf, 100e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_period_constraint(clk100_buf, 1e9/100e6, 0)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq, 0)
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platform.add_false_path_constraints(clk100_buf, self.cd_sys.clk)
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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def __init__(self, sys_clk_freq=int(60e6), with_ethernet=False, with_etherbone=False, **kwargs):
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platform = arty_symbiflow.Platform()
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, clk_freq=sys_clk_freq, **kwargs)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.submodules.leds = LedChaser(
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pads = Cat(*[platform.request("user_led", i) for i in range(4)]),
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sys_clk_freq = sys_clk_freq)
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self.add_csr("leds")
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on Arty A7")
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parser.add_argument("--build", action="store_true", help="Build bitstream")
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parser.add_argument("--load", action="store_true", help="Load bitstream")
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builder_args(parser)
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soc_core_args(parser)
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symbiflow_build_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(**soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build(**symbiflow_build_argdict(args), run=args.build)
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if args.load:
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prog = soc.platform.create_programmer()
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prog.load_bitstream(os.path.join(builder.gateware_dir, soc.build_name + ".bit"))
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if __name__ == "__main__":
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main()
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@ -5,7 +5,7 @@
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import os
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from litex.build.generic_platform import GenericPlatform
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from litex.build.xilinx import common, vivado, ise
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from litex.build.xilinx import common, vivado, ise, symbiflow
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# XilinxPlatform -----------------------------------------------------------------------------------
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@ -20,6 +20,8 @@ class XilinxPlatform(GenericPlatform):
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self.toolchain = ise.XilinxISEToolchain()
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elif toolchain == "vivado":
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self.toolchain = vivado.XilinxVivadoToolchain()
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elif toolchain == "symbiflow":
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self.toolchain = symbiflow.SymbiflowToolchain()
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else:
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raise ValueError("Unknown toolchain")
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@ -0,0 +1,321 @@
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# This file is Copyright (c) 2014-2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# This file is Copyright (c) 2020 Antmicro <www.antmicro.com>
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# License: BSD
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import os
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import subprocess
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import sys
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import math
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from typing import NamedTuple, Union, List
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import re
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from migen.fhdl.structure import _Fragment, wrap, Constant
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from migen.fhdl.specials import Instance
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from litex.build.generic_platform import *
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from litex.build import tools
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def _unwrap(value):
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return value.value if isinstance(value, Constant) else value
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# Constraints (.xdc) -------------------------------------------------------------------------------
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def _xdc_separator(msg):
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r = "#"*80 + "\n"
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r += "# " + msg + "\n"
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r += "#"*80 + "\n"
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return r
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def _format_xdc_constraint(c):
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if isinstance(c, Pins):
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return "set_property LOC " + c.identifiers[0]
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elif isinstance(c, IOStandard):
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return "set_property IOSTANDARD " + c.name
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elif isinstance(c, Drive):
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return "set_property DRIVE " + str(c.strength)
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elif isinstance(c, Misc):
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return "set_property " + c.misc.replace("=", " ")
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elif isinstance(c, Inverted):
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return None
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else:
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raise ValueError("unknown constraint {}".format(c))
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def _format_xdc(signame, resname, *constraints):
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fmt_c = [_format_xdc_constraint(c) for c in constraints]
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fmt_r = resname[0] + ":" + str(resname[1])
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if resname[2] is not None:
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fmt_r += "." + resname[2]
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r = "# {}\n".format(fmt_r)
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for c in fmt_c:
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if c is not None:
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r += c + " [get_ports {" + signame + "}]\n"
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r += "\n"
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return r
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def _build_xdc(named_sc):
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r = ""
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for sig, pins, others, resname in named_sc:
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if len(pins) > 1:
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for i, p in enumerate(pins):
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r += _format_xdc(sig + "[" + str(i) + "]", resname, Pins(p), *others)
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elif pins:
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r += _format_xdc(sig, resname, Pins(pins[0]), *others)
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else:
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r += _format_xdc(sig, resname, *others)
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return r
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# PCF ----------------------------------------------------------------------------------------------
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def _build_pcf(named_sc):
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r = ""
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current_resname = ""
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for sig, pins, _, resname in named_sc:
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if current_resname != resname[0]:
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if current_resname:
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r += "\n"
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current_resname = resname[0]
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r += f"# {current_resname}\n"
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if len(pins) > 1:
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for i, p in enumerate(pins):
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r += f"set_io {sig}[{i}] {Pins(p).identifiers[0]}\n"
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elif pins:
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r += f"set_io {sig} {Pins(pins[0]).identifiers[0]}\n"
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return r
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# SDC ----------------------------------------------------------------------------------------------
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def _build_sdc(named_pc):
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return "\n".join(named_pc) if named_pc else ""
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# Makefile -----------------------------------------------------------------------------------------
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class _MakefileGenerator:
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class Var(NamedTuple):
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name: str
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value: Union[str, List[str]] = ""
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class Rule(NamedTuple):
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target: str
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prerequisites: List[str] = []
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commands: List[str] = []
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phony: bool = False
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def __init__(self, ast):
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self.ast = ast
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def generate(self):
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makefile = []
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for entry in self.ast:
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if isinstance(entry, str):
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makefile.append(entry)
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elif isinstance(entry, self.Var):
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if not entry.value:
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makefile.append(f"{entry.name} :=")
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elif isinstance(entry.value, list):
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indent = " " * (len(entry.name) + len(" := "))
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line = f"{entry.name} := {entry.value[0]}"
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for value in entry.value[1:]:
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line += " \\"
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makefile.append(line)
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line = indent + value
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makefile.append(line)
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elif isinstance(entry.value, str):
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makefile.append(f"{entry.name} := {entry.value}")
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else:
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raise
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elif isinstance(entry, self.Rule):
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makefile.append("")
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if entry.phony:
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makefile.append(f".PHONY: {entry.target}")
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makefile.append(" ".join([f"{entry.target}:", *entry.prerequisites]))
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for cmd in entry.commands:
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makefile.append(f"\t{cmd}")
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return "\n".join(makefile)
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def _run_make():
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if tools.subprocess_call_filtered("make", []) != 0:
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raise OSError("Subprocess failed")
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# SymbiflowToolchain -------------------------------------------------------------------------------
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class SymbiflowToolchain:
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attr_translate = {
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"keep": ("dont_touch", "true"),
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"no_retiming": ("dont_touch", "true"),
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"async_reg": ("async_reg", "true"),
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"mr_ff": ("mr_ff", "true"), # user-defined attribute
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"ars_ff1": ("ars_ff1", "true"), # user-defined attribute
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"ars_ff2": ("ars_ff2", "true"), # user-defined attribute
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"no_shreg_extract": None
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}
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def __init__(self):
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self.clocks = dict()
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self.false_paths = set()
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self.symbiflow_device = None
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self.bitstream_device = None
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def _check_properties(self, platform):
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if not self.symbiflow_device:
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raise ValueError(f"symbiflow_device is not specified")
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if not self.bitstream_device:
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try:
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self.bitstream_device = {
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"xc7a": "artix7"
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}[platform.device[:4]]
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except KeyError:
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raise ValueError(f"Unsupported device: {platform.device}")
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def _generate_makefile(self, platform, build_name):
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Var = _MakefileGenerator.Var
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Rule = _MakefileGenerator.Rule
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makefile = _MakefileGenerator([
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"# Autogenerated by LiteX / git: " + tools.get_litex_git_revision() + "\n",
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Var("TOP", build_name),
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Var("PARTNAME", platform.device),
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Var("DEVICE", self.symbiflow_device),
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Var("BITSTREAM_DEVICE", self.bitstream_device),
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"",
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Var("VERILOG", [f for f,language,_ in platform.sources if language in ["verilog", "system_verilog"]]),
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Var("MEM_INIT", [f"{name}" for name in os.listdir() if name.endswith(".init")]),
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Var("PCF", f"{build_name}.pcf"),
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Var("SDC", f"{build_name}.sdc"),
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Var("XDC", f"{build_name}.xdc"),
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Var("ARTIFACTS", [
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"$(TOP).eblif", "$(TOP).frames", "$(TOP).ioplace", "$(TOP).net",
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"$(TOP).place", "$(TOP).route", "$(TOP)_synth.*",
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"*.bit", "*.fasm", "*.json", "*.log", "*.rpt",
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"constraints.place"
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]),
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Rule("all", ["$(TOP).bit"], phony=True),
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Rule("$(TOP).eblif", ["$(VERILOG)", "$(MEM_INIT)", "$(XDC)"], commands=[
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"synth -t $(TOP) -v $(VERILOG) -d $(BITSTREAM_DEVICE) -p $(PARTNAME) -x $(XDC) > /dev/null"
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]),
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Rule("$(TOP).net", ["$(TOP).eblif", "$(SDC)"], commands=[
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"pack -e $(TOP).eblif -d $(DEVICE) -s $(SDC) > /dev/null"
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]),
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Rule("$(TOP).place", ["$(TOP).net", "$(PCF)"], commands=[
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"place -e $(TOP).eblif -d $(DEVICE) -p $(PCF) -n $(TOP).net -P $(PARTNAME) -s $(SDC) > /dev/null"
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]),
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Rule("$(TOP).route", ["$(TOP).place"], commands=[
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"route -e $(TOP).eblif -d $(DEVICE) -s $(SDC) > /dev/null"
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]),
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Rule("$(TOP).fasm", ["$(TOP).route"], commands=[
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"write_fasm -e $(TOP).eblif -d $(DEVICE) > /dev/null"
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]),
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Rule("$(TOP).bit", ["$(TOP).fasm"], commands=[
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"write_bitstream -d $(BITSTREAM_DEVICE) -f $(TOP).fasm -p $(PARTNAME) -b $(TOP).bit > /dev/null"
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]),
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Rule("clean", phony=True, commands=[
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"rm -f $(ARTIFACTS)"
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]),
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])
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tools.write_to_file("Makefile", makefile.generate())
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def _build_clock_constraints(self, platform):
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for clk, (period, phase) in sorted(self.clocks.items(), key=lambda x: x[0].duid):
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rising_edge = math.floor(period/360.0 * phase * 1e3)/1e3
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falling_edge = math.floor(((rising_edge + period/2) % period) * 1.e3)/1e3
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platform.add_platform_command(f"create_clock -period {period} {{clk}} -waveform {{{{{rising_edge} {falling_edge}}}}}", clk=clk)
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for from_, to in sorted(self.false_paths, key=lambda x: (x[0].duid, x[1].duid)):
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platform.add_platform_command("set_clock_groups -exclusive -group {{{from_}}} -group {{{to}}}", from_=from_, to=to)
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# Make sure add_*_constraint cannot be used again
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del self.clocks
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del self.false_paths
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# Yosys has limited support for real type. It requires that some values be multiplied
|
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# by 1000 and passed as integers. For details, see:
|
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# https://github.com/SymbiFlow/symbiflow-arch-defs/blob/master/xc/xc7/techmap/cells_map.v
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def _fix_instance(self, instance):
|
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if instance.of == "PLLE2_ADV":
|
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for item in instance.items:
|
||||
if isinstance(item, Instance.Parameter) and re.fullmatch("CLKOUT[0-9]_(PHASE|DUTY_CYCLE)", item.name):
|
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item.value = wrap(math.floor(_unwrap(item.value) * 1000))
|
||||
|
||||
def build(self, platform, fragment,
|
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build_dir = "build",
|
||||
build_name = "top",
|
||||
run = True,
|
||||
enable_xpm = False,
|
||||
**kwargs):
|
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|
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self._check_properties(platform)
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||||
|
||||
# Create build directory
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os.makedirs(build_dir, exist_ok=True)
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cwd = os.getcwd()
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os.chdir(build_dir)
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# Finalize design
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if not isinstance(fragment, _Fragment):
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fragment = fragment.get_fragment()
|
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platform.finalize(fragment)
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||||
# Symbiflow-specific fixes
|
||||
for instance in fragment.specials:
|
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if isinstance(instance, Instance):
|
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self._fix_instance(instance)
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# Generate timing constraints
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self._build_clock_constraints(platform)
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||||
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# Generate verilog
|
||||
v_output = platform.get_verilog(fragment, name=build_name, **kwargs)
|
||||
named_sc, named_pc = platform.resolve_signals(v_output.ns)
|
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v_file = build_name + ".v"
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||||
v_output.write(v_file)
|
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platform.add_source(v_file)
|
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|
||||
self._generate_makefile(
|
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platform = platform,
|
||||
build_name = build_name
|
||||
)
|
||||
|
||||
# Generate design constraints
|
||||
tools.write_to_file(build_name + ".xdc", _build_xdc(named_sc))
|
||||
tools.write_to_file(build_name + ".pcf", _build_pcf(named_sc))
|
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tools.write_to_file(build_name + ".sdc", _build_sdc(named_pc))
|
||||
|
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if run:
|
||||
_run_make()
|
||||
|
||||
os.chdir(cwd)
|
||||
|
||||
return v_output.ns
|
||||
|
||||
def add_period_constraint(self, platform, clk, period, phase=0):
|
||||
clk.attr.add("keep")
|
||||
phase = math.floor(phase % 360.0 * 1e3)/1e3
|
||||
period = math.floor(period*1e3)/1e3 # round to lowest picosecond
|
||||
if clk in self.clocks:
|
||||
if period != self.clocks[clk][0]:
|
||||
raise ValueError("Clock already constrained to {:.2f}ns, new constraint to {:.2f}ns"
|
||||
.format(self.clocks[clk][0], period))
|
||||
if phase != self.clocks[clk][1]:
|
||||
raise ValueError("Clock already constrained with phase {:.2f}deg, new phase {:.2f}deg"
|
||||
.format(self.clocks[clk][1], phase))
|
||||
self.clocks[clk] = (period, phase)
|
||||
|
||||
def add_false_path_constraint(self, platform, from_, to):
|
||||
if (from_, to) in self.false_paths or (to, from_) in self.false_paths:
|
||||
return
|
||||
from_.attr.add("keep")
|
||||
to.attr.add("keep")
|
||||
self.false_paths.add((from_, to))
|
||||
|
||||
|
||||
def symbiflow_build_args(parser):
|
||||
pass
|
||||
|
||||
|
||||
def symbiflow_build_argdict(args):
|
||||
return dict()
|
||||
|
|
@ -73,6 +73,13 @@ class TestTargets(unittest.TestCase):
|
|||
])
|
||||
self.assertEqual(errors, 0)
|
||||
|
||||
def test_arty_symbiflow(self):
|
||||
from litex.boards.targets.arty_symbiflow import BaseSoC
|
||||
errors = build_test([
|
||||
BaseSoC(**test_kwargs)
|
||||
])
|
||||
self.assertEqual(errors, 0)
|
||||
|
||||
# Kintex-7
|
||||
def test_genesys2(self):
|
||||
from litex.boards.targets.genesys2 import BaseSoC
|
||||
|
|
@ -112,21 +119,21 @@ class TestTargets(unittest.TestCase):
|
|||
def test_simple(self):
|
||||
platforms = []
|
||||
# Xilinx
|
||||
platforms += ["minispartan6"] # Spartan6
|
||||
platforms += ["arty", "netv2", "nexys4ddr", "nexys_video"] # Artix7
|
||||
platforms += ["kc705", "genesys2"] # Kintex7
|
||||
platforms += ["kcu105"] # Kintex Ultrascale
|
||||
platforms += ["minispartan6"] # Spartan6
|
||||
platforms += ["arty", "netv2", "nexys4ddr", "nexys_video", "arty_symbiflow"] # Artix7
|
||||
platforms += ["kc705", "genesys2"] # Kintex7
|
||||
platforms += ["kcu105"] # Kintex Ultrascale
|
||||
|
||||
# Altera/Intel
|
||||
platforms += ["de0nano"] # Cyclone4
|
||||
platforms += ["de0nano"] # Cyclone4
|
||||
|
||||
# Lattice
|
||||
platforms += ["tinyfpga_bx"] # iCE40
|
||||
platforms += ["machxo3"] # MachXO3
|
||||
platforms += ["versa_ecp5", "ulx3s"] # ECP5
|
||||
platforms += ["tinyfpga_bx"] # iCE40
|
||||
platforms += ["machxo3"] # MachXO3
|
||||
platforms += ["versa_ecp5", "ulx3s"] # ECP5
|
||||
|
||||
# Microsemi
|
||||
platforms += ["avalanche"] # PolarFire
|
||||
platforms += ["avalanche"] # PolarFire
|
||||
|
||||
for p in platforms:
|
||||
with self.subTest(platform=p):
|
||||
|
|
|
|||
Loading…
Reference in New Issue