Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

cpu/vexriscv: Fix missing add_soc_component update.

This commit is contained in:
Florent Kermarrec 2023-02-21 10:37:09 +01:00
parent 45b9636902
commit 51326b93a5
1 changed files with 6 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
litex/soc/cores/cpu/vexriscv/core.py
View File

@ -15,8 +15,12 @@ import os
from migen import * from migen import *
from litex import get_data_mod from litex import get_data_mod
from litex.soc.interconnect import wishbone from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import * from litex.soc.interconnect.csr import *
from litex.soc.integration.soc import SoCRegion
from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV32
# Variants ----------------------------------------------------------------------------------------- # Variants -----------------------------------------------------------------------------------------
@ -334,11 +338,11 @@ class VexRiscv(CPU, AutoCSR):
vdir = get_data_mod("cpu", "vexriscv").data_location vdir = get_data_mod("cpu", "vexriscv").data_location
platform.add_source(os.path.join(vdir, cpu_filename)) platform.add_source(os.path.join(vdir, cpu_filename))
def add_soc_components(self, soc, soc_region_cls): def add_soc_components(self, soc):
# Connect Debug interface to SoC. # Connect Debug interface to SoC.
if "debug" in self.variant: if "debug" in self.variant:
soc.bus.add_slave("vexriscv_debug", self.debug_bus, region= soc.bus.add_slave("vexriscv_debug", self.debug_bus, region=
soc_region_cls( SoCRegion(
origin = soc.mem_map.get("vexriscv_debug"), origin = soc.mem_map.get("vexriscv_debug"),
size = 0x100, size = 0x100,
cached = False cached = False