dvisampler: character synchronization
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@ -5,6 +5,7 @@ from migen.bank.description import *
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from milkymist.dvisampler.edid import EDID
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from milkymist.dvisampler.edid import EDID
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from milkymist.dvisampler.clocking import Clocking
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from milkymist.dvisampler.clocking import Clocking
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from milkymist.dvisampler.datacapture import DataCapture
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from milkymist.dvisampler.datacapture import DataCapture
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from milkymist.dvisampler.charsync import CharSync
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class DVISampler(Module, AutoReg):
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class DVISampler(Module, AutoReg):
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def __init__(self, inversions=""):
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def __init__(self, inversions=""):
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@ -18,13 +19,18 @@ class DVISampler(Module, AutoReg):
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for datan in "012":
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for datan in "012":
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name = "data" + str(datan)
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name = "data" + str(datan)
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invert = datan in inversions
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invert = datan in inversions
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signame = name + "_n" if invert else name
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s = Signal(name=signame)
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setattr(self, signame, s)
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cap = DataCapture(8, invert)
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cap = DataCapture(8, invert)
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setattr(self.submodules, name + "_cap", cap)
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setattr(self.submodules, name + "_cap", cap)
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if invert:
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name += "_n"
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s = Signal(name=name)
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setattr(self, name, s)
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self.comb += [
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self.comb += [
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cap.pad.eq(s),
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cap.pad.eq(s),
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cap.serdesstrobe.eq(self.clocking.serdesstrobe)
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cap.serdesstrobe.eq(self.clocking.serdesstrobe)
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]
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]
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charsync = CharSync()
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setattr(self.submodules, name + "_charsync", charsync)
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self.comb += charsync.raw_data.eq(cap.d)
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@ -0,0 +1,51 @@
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from migen.fhdl.structure import *
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from migen.fhdl.module import Module
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from migen.genlib.cdc import MultiReg
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from migen.genlib.misc import optree
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from migen.bank.description import *
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_control_tokens = [0b1101010100, 0b0010101011, 0b0101010100, 0b1010101011]
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class CharSync(Module, AutoReg):
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def __init__(self, required_controls=8):
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self.raw_data = Signal(10)
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self.char_synced = Signal()
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self.data = Signal(10)
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self._r_char_synced = RegisterField(1, READ_ONLY, WRITE_ONLY)
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###
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raw_data1 = Signal(10)
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self.sync.pix += raw_data1.eq(self.raw_data)
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raw = Signal(20)
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self.comb += raw.eq(Cat(raw_data1, self.raw_data))
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found_control = Signal()
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control_position = Signal(max=10)
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for i in range(10):
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self.sync.pix += If(optree("|", [raw[i:i+10] == t for t in _control_tokens]),
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found_control.eq(1),
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control_position.eq(i)
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)
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control_counter = Signal(max=required_controls)
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previous_control_position = Signal(max=10)
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word_sel = Signal(max=10)
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self.sync.pix += [
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If(found_control & (control_position == previous_control_position),
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If(control_counter == (required_controls - 1),
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control_counter.eq(0),
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self.char_synced.eq(1),
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word_sel.eq(control_position)
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).Else(
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control_counter.eq(control_counter + 1)
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)
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).Else(
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control_counter.eq(0)
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),
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previous_control_position.eq(control_position)
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]
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self.specials += MultiReg(self.char_synced, self._r_char_synced.field.w)
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self.sync.pix += self.data.eq(raw >> word_sel)
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@ -13,16 +13,19 @@
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#define CSR_DVISAMPLER0_D0_DELAY_BUSY DVISAMPLER0_CSR(0x0C)
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#define CSR_DVISAMPLER0_D0_DELAY_BUSY DVISAMPLER0_CSR(0x0C)
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#define CSR_DVISAMPLER0_D0_PHASE DVISAMPLER0_CSR(0x10)
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#define CSR_DVISAMPLER0_D0_PHASE DVISAMPLER0_CSR(0x10)
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#define CSR_DVISAMPLER0_D0_PHASE_RESET DVISAMPLER0_CSR(0x14)
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#define CSR_DVISAMPLER0_D0_PHASE_RESET DVISAMPLER0_CSR(0x14)
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#define CSR_DVISAMPLER0_D0_CHAR_SYNCED DVISAMPLER0_CSR(0x18)
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#define CSR_DVISAMPLER0_D1_DELAY_CTL DVISAMPLER0_CSR(0x18)
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#define CSR_DVISAMPLER0_D1_DELAY_CTL DVISAMPLER0_CSR(0x1C)
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#define CSR_DVISAMPLER0_D1_DELAY_BUSY DVISAMPLER0_CSR(0x1C)
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#define CSR_DVISAMPLER0_D1_DELAY_BUSY DVISAMPLER0_CSR(0x20)
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#define CSR_DVISAMPLER0_D1_PHASE DVISAMPLER0_CSR(0x20)
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#define CSR_DVISAMPLER0_D1_PHASE DVISAMPLER0_CSR(0x24)
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#define CSR_DVISAMPLER0_D1_PHASE_RESET DVISAMPLER0_CSR(0x24)
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#define CSR_DVISAMPLER0_D1_PHASE_RESET DVISAMPLER0_CSR(0x28)
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#define CSR_DVISAMPLER0_D1_CHAR_SYNCED DVISAMPLER0_CSR(0x2C)
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#define CSR_DVISAMPLER0_D2_DELAY_CTL DVISAMPLER0_CSR(0x28)
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#define CSR_DVISAMPLER0_D2_DELAY_CTL DVISAMPLER0_CSR(0x30)
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#define CSR_DVISAMPLER0_D2_DELAY_BUSY DVISAMPLER0_CSR(0x2C)
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#define CSR_DVISAMPLER0_D2_DELAY_BUSY DVISAMPLER0_CSR(0x34)
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#define CSR_DVISAMPLER0_D2_PHASE DVISAMPLER0_CSR(0x30)
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#define CSR_DVISAMPLER0_D2_PHASE DVISAMPLER0_CSR(0x38)
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#define CSR_DVISAMPLER0_D2_PHASE_RESET DVISAMPLER0_CSR(0x34)
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#define CSR_DVISAMPLER0_D2_PHASE_RESET DVISAMPLER0_CSR(0x3C)
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#define CSR_DVISAMPLER0_D2_CHAR_SYNCED DVISAMPLER0_CSR(0x40)
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#define DVISAMPLER_DELAY_CAL 0x01
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#define DVISAMPLER_DELAY_CAL 0x01
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#define DVISAMPLER_DELAY_RST 0x02
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#define DVISAMPLER_DELAY_RST 0x02
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@ -60,7 +60,10 @@ static void adjust_phase(void)
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CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
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CSR_DVISAMPLER0_D2_PHASE_RESET = 1;
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break;
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break;
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}
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}
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//printf("Ph: %4d %4d %4d\n", d0, d1, d2);
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printf("Ph: %4d %4d %4d // %d%d%d\n", d0, d1, d2,
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CSR_DVISAMPLER0_D0_CHAR_SYNCED,
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CSR_DVISAMPLER0_D1_CHAR_SYNCED,
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CSR_DVISAMPLER0_D2_CHAR_SYNCED);
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}
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}
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static void vmix(void)
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static void vmix(void)
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