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integration/soc: review/simplify interconnect and add logger.info.

This commit is contained in:
Florent Kermarrec 2020-05-13 18:26:54 +02:00
parent 78413cc09e
commit 51742be2bb
1 changed files with 21 additions and 21 deletions
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42
litex/soc/integration/soc.py
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@ -822,27 +822,27 @@ class SoC(Module):
self.logger.info(colorer("-"*80, color="bright")) self.logger.info(colorer("-"*80, color="bright"))
# SoC Bus Interconnect --------------------------------------------------------------------- # SoC Bus Interconnect ---------------------------------------------------------------------
bus_masters = self.bus.masters.values() if len(self.bus.masters) and len(self.bus.slaves):
bus_slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()] # If 1 bus_master, 1 bus_slave and no address translation, use InterconnectPointToPoint.
if ((len(self.bus.masters) == 1) and
use_p2p = False (len(self.bus.slaves) == 1) and
if len(bus_masters) == 1 and len(bus_slaves) == 1: (next(iter(self.bus.regions.values())).origin == 0)):
n = list(self.bus.slaves)[0] self.submodules.bus_interconnect = wishbone.InterconnectPointToPoint(
if self.bus.regions[n].origin == 0: master = next(iter(self.bus.masters.values())),
use_p2p = True slave = next(iter(self.bus.slaves.values())))
# Otherwise, use InterconnectShared.
if use_p2p: else:
self.submodules.bus_interconnect = wishbone.InterconnectPointToPoint( self.submodules.bus_interconnect = wishbone.InterconnectShared(
master = list(bus_masters)[0], masters = self.bus.masters.values(),
slave = list(self.bus.slaves.values())[0]) slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()],
elif len(bus_masters) and len(bus_slaves): register = True,
self.submodules.bus_interconnect = wishbone.InterconnectShared( timeout_cycles = self.bus.timeout)
masters = bus_masters, if hasattr(self, "ctrl") and self.bus.timeout is not None:
slaves = bus_slaves, self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
register = True, self.bus.logger.info("Interconnect: {} ({} <-> {}).".format(
timeout_cycles = self.bus.timeout) colorer(self.bus_interconnect.__class__.__name__),
if hasattr(self, "ctrl") and self.bus.timeout is not None: colorer(len(self.bus.masters)),
self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error) colorer(len(self.bus.slaves))))
# SoC CSR Interconnect --------------------------------------------------------------------- # SoC CSR Interconnect ---------------------------------------------------------------------
self.submodules.csr_bankarray = csr_bus.CSRBankArray(self, self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,