sim: remove PureSimulable (superseded by Module)

examples/sim/fir.py

@@ -6,10 +6,11 @@ from scipy import signal
 import matplotlib.pyplot as plt
 
 from migen.fhdl.structure import *
+from migen.fhdl.module import Module
 from migen.fhdl import verilog
 from migen.genlib.misc import optree
 from migen.fhdl import autofragment
-from migen.sim.generic import Simulator, PureSimulable
+from migen.sim.generic import Simulator
 
 # A synthesizable FIR filter.
 class FIR:
@@ -36,7 +37,7 @@ class FIR:
 
 # A test bench for our FIR filter.
 # Generates a sine wave at the input and records the output.
-class TB(PureSimulable):
+class TB(Module):
 	def __init__(self, fir, frequency):
 		self.fir = fir
 		self.frequency = frequency

migen/actorlib/sim.py

@@ -1,7 +1,7 @@
 from migen.fhdl.structure import *
+from migen.fhdl.module import Module
 from migen.flow.actor import *
 from migen.flow.transactions import *
-from migen.sim.generic import PureSimulable
 
 # Generators yield None or a tuple of Tokens.
 # Tokens for Sink endpoints are pulled and the "value" field filled in.
@@ -9,7 +9,7 @@ from migen.sim.generic import PureSimulable
 #
 # NB: the possibility to push several tokens at once is important to interact
 # with actors that only accept a group of tokens when all of them are available.
-class TokenExchanger(PureSimulable):
+class TokenExchanger(Module):
 	def __init__(self, generator, actor):
 		self.generator = generator
 		self.actor = actor

migen/bus/csr.py

@@ -1,8 +1,8 @@
 from migen.fhdl.structure import *
 from migen.fhdl.specials import Memory
+from migen.fhdl.module import Module
 from migen.bus.simple import *
 from migen.bus.transactions import *
-from migen.sim.generic import PureSimulable
 from migen.bank.description import RegisterField
 from migen.genlib.misc import chooser
 
@@ -19,7 +19,7 @@ class Interface(SimpleInterface):
 class Interconnect(SimpleInterconnect):
 	pass
 
-class Initiator(PureSimulable):
+class Initiator(Module):
 	def __init__(self, generator, bus=None):
 		self.generator = generator
 		if bus is None:

migen/bus/memory.py

@@ -1,5 +1,5 @@
+from migen.fhdl.module import Module
 from migen.bus.transactions import *
-from migen.sim.generic import PureSimulable
 
 def _byte_mask(orig, dat_w, sel):
 	r = 0
@@ -15,7 +15,7 @@ def _byte_mask(orig, dat_w, sel):
 		shift += 8
 	return r
 
-class Initiator(PureSimulable):
+class Initiator(Module):
 	def __init__(self, generator, mem):
 		self.generator = generator
 		self.mem = mem

migen/bus/wishbone.py

@@ -1,10 +1,11 @@
 from migen.fhdl.structure import *
 from migen.fhdl.specials import Memory
+from migen.fhdl.module import Module
 from migen.genlib import roundrobin
 from migen.genlib.misc import optree
 from migen.bus.simple import *
 from migen.bus.transactions import *
-from migen.sim.generic import Proxy, PureSimulable
+from migen.sim.generic import Proxy
 
 _desc = Description(
 	(M_TO_S,	"adr",		30),
@@ -116,7 +117,7 @@ class InterconnectShared:
 	def get_fragment(self):
 		return self._arbiter.get_fragment() + self._decoder.get_fragment()
 
-class Tap(PureSimulable):
+class Tap(Module):
 	def __init__(self, bus, handler=print):
 		self.bus = bus
 		self.handler = handler
@@ -133,7 +134,7 @@ class Tap(PureSimulable):
 					s.rd(self.bus.dat_r))
 			self.handler(transaction)
 
-class Initiator(PureSimulable):
+class Initiator(Module):
 	def __init__(self, generator, bus=None):
 		self.generator = generator
 		if bus is None:
@@ -180,7 +181,7 @@ class TargetModel:
 	def can_ack(self, bus):
 		return True
 
-class Target(PureSimulable):
+class Target(Module):
 	def __init__(self, model, bus=None):
 		if bus is None:
 			bus = Interface()

migen/flow/hooks.py

@@ -1,8 +1,8 @@
 from migen.fhdl.structure import *
+from migen.fhdl.module import Module
 from migen.flow.actor import *
-from migen.sim.generic import PureSimulable
 
-class EndpointSimHook(PureSimulable):
+class EndpointSimHook(Module):
 	def __init__(self, endpoint):
 		self.endpoint = endpoint
 	

migen/sim/generic.py

@@ -203,10 +203,3 @@ class Proxy:
 		item = getattr(self._obj, name)
 		assert(isinstance(item, Signal))
 		self._sim.wr(item, value)
-
-class PureSimulable:
-	def do_simulation(self, s):
-		raise NotImplementedError("Need to overload do_simulation")
-	
-	def get_fragment(self):
-		return Fragment(sim=[self.do_simulation])