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soc/add_spi_flash: default clk_freq to 20MHz 

This is safer than defaulting to sys_clock / 2 if sys_clock > 100MHz
clk_freq tuning will result in a faster clock if supported by hardware.
This commit is contained in:
Andrew Dennison 2024-02-01 10:01:15 +11:00
parent 1dddfa6841
commit 51c3cb3552
1 changed files with 1 additions and 2 deletions
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3
litex/soc/integration/soc.py
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@ -1879,7 +1879,7 @@ class LiteXSoC(SoC):
self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface. self.add_constant("ETH_PHY_NO_RESET") # Disable reset from BIOS to avoid disabling Hardware Interface.
# Add SPI Flash -------------------------------------------------------------------------------- # Add SPI Flash --------------------------------------------------------------------------------
def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=None, module=None, phy=None, rate="1:1", software_debug=False, **kwargs): def add_spi_flash(self, name="spiflash", mode="4x", clk_freq=20e6, module=None, phy=None, rate="1:1", software_debug=False, **kwargs):
# Imports. # Imports.
from litespi import LiteSPI from litespi import LiteSPI
from litespi.phy.generic import LiteSPIPHY from litespi.phy.generic import LiteSPIPHY
@ -1888,7 +1888,6 @@ class LiteXSoC(SoC):
# Checks/Parameters. # Checks/Parameters.
assert mode in ["1x", "4x"] assert mode in ["1x", "4x"]
if clk_freq is None: clk_freq = self.sys_clk_freq
# From LiteSPIClkGen: clk_freq will be ``sys_clk_freq/(2*(1+div))``. # From LiteSPIClkGen: clk_freq will be ``sys_clk_freq/(2*(1+div))``.
default_divisor = math.ceil(self.sys_clk_freq/(clk_freq*2))-1 default_divisor = math.ceil(self.sys_clk_freq/(clk_freq*2))-1
clk_freq = int(self.sys_clk_freq/(2*(1+default_divisor))) clk_freq = int(self.sys_clk_freq/(2*(1+default_divisor)))