litescope: pep8 (E231)
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@ -4,7 +4,7 @@ from misoclib.tools.litescope.host.driver.reg import *
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def write_b(uart, data):
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uart.write(pack('B',data))
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uart.write(pack('B', data))
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class LiteScopeUARTDriver:
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@ -109,5 +109,5 @@ class Dump:
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def __len__(self):
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l = 0
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for var in self.vars:
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l = max(len(var),l)
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l = max(len(var), l)
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return l
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@ -46,8 +46,8 @@ class CSVDump(Dump):
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if __name__ == '__main__':
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dump = CSVDump()
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dump.add(Var("foo1", 1, [0,1,0,1,0,1]))
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dump.add(Var("foo2", 2, [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
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dump.add(Var("foo1", 1, [0, 1, 0, 1, 0, 1]))
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dump.add(Var("foo2", 2, [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]))
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ramp = [i%128 for i in range(1024)]
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dump.add(Var("ramp", 16, ramp))
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dump.write("dump.csv")
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@ -27,8 +27,8 @@ class PythonDump(Dump):
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if __name__ == '__main__':
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dump = PythonDump()
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dump.add(Var("foo1", 1, [0,1,0,1,0,1]))
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dump.add(Var("foo2", 2, [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
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dump.add(Var("foo1", 1, [0, 1, 0, 1, 0, 1]))
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dump.add(Var("foo2", 2, [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]))
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ramp = [i%128 for i in range(1024)]
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dump.add(Var("ramp", 16, ramp))
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dump.write("dump.py")
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@ -141,8 +141,8 @@ samplerate = {} KHz
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if __name__ == '__main__':
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dump = SigrokDump()
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dump.add(Var("foo1", 1, [0,1,0,1,0,1]))
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dump.add(Var("foo2", 2, [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
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dump.add(Var("foo1", 1, [0, 1, 0, 1, 0, 1]))
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dump.add(Var("foo2", 2, [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]))
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ramp = [i%128 for i in range(1024)]
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dump.add(Var("ramp", 16, ramp))
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dump.write("dump.sr")
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@ -121,8 +121,8 @@ class VCDDump(Dump):
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if __name__ == '__main__':
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dump = VCDDump()
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dump.add(Var("foo1", 1, [0,1,0,1,0,1]))
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dump.add(Var("foo2", 2, [1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0,1,0]))
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dump.add(Var("foo1", 1, [0, 1, 0, 1, 0, 1]))
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dump.add(Var("foo2", 2, [1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0, 1, 0]))
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ramp = [i%128 for i in range(1024)]
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dump.add(Var("ramp", 16, ramp))
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dump.write("dump.vcd")
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