cpu: Add initial Cortex-M1 support.
Can be tested with targets from LiteX-Boards and Cortex-M1 sources in execution path:
python3 -m litex_boards.targets.digilent_arty --cpu-type=cortex_m1 --build --load
__ _ __ _ __
/ / (_) /____ | |/_/
/ /__/ / __/ -_)> <
/____/_/\__/\__/_/|_|
Build your hardware, easily!
(c) Copyright 2012-2022 Enjoy-Digital
(c) Copyright 2007-2015 M-Labs
BIOS built on Apr 22 2022 15:04:52
BIOS CRC passed (5773c241)
LiteX git sha1: 6b3a5412
--=============== SoC ==================--
CPU: ARM Cortex-M1 @ 100MHz
BUS: WISHBONE 32-bit @ 4GiB
CSR: 32-bit data
ROM: 128KiB
SRAM: 8KiB
L2: 8KiB
SDRAM: 262144KiB 16-bit @ 800MT/s (CL-7 CWL-5)
--========== Initialization ============--
Initializing SDRAM @0x10000000...
Switching SDRAM to software control.
Read leveling:
m0, b00: |00000000000000000000000000000000| delays: -
m0, b01: |00000000000000000000000000000000| delays: -
m0, b02: |11111111110000000000000000000000| delays: 05+-05
m0, b03: |00000000000011111111111111000000| delays: 19+-07
m0, b04: |00000000000000000000000000011111| delays: 30+-02
m0, b05: |00000000000000000000000000000000| delays: -
m0, b06: |00000000000000000000000000000000| delays: -
m0, b07: |00000000000000000000000000000000| delays: -
best: m0, b03 delays: 19+-07
m1, b00: |00000000000000000000000000000000| delays: -
m1, b01: |00000000000000000000000000000000| delays: -
m1, b02: |11111111110000000000000000000000| delays: 05+-05
m1, b03: |00000000000011111111111111000000| delays: 19+-07
m1, b04: |00000000000000000000000000001111| delays: 30+-02
m1, b05: |00000000000000000000000000000000| delays: -
m1, b06: |00000000000000000000000000000000| delays: -
m1, b07: |00000000000000000000000000000000| delays: -
best: m1, b03 delays: 19+-07
Switching SDRAM to hardware control.
Memtest at 0x10000000 (2.0MiB)...
Write: 0x10000000-0x10200000 2.0MiB
Read: 0x10000000-0x10200000 2.0MiB
Memtest OK
Memspeed at 0x10000000 (Sequential, 2.0MiB)...
Write speed: 16.5MiB/s
Read speed: 19.3MiB/s
--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
Timeout
No boot medium found
--============= Console ================--
litex>
This commit is contained in:
Ilia Sergachev
Florent Kermarrec
parent
016e1abcff
commit
51eb310b0e
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@ -0,0 +1 @@
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from litex.soc.cores.cpu.cortex_m1.core import CortexM1
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@ -0,0 +1,5 @@
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void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr);
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void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr) {
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goto *addr;
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}
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@ -0,0 +1,107 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2022 Ilia Sergachev <ilia@sergachev.ch>
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# SPDX-License-Identifier: BSD-2-Clause
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import os
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from migen import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU
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from litex.soc.interconnect import axi
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class CortexM1(CPU):
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variants = ["standard"]
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family = "arm"
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name = "cortex_m1"
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human_name = "ARM Cortex-M1"
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data_width = 32
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endianness = "little"
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reset_address = 0x0000_0000
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gcc_triple = "arm-none-eabi"
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gcc_flags = "-march=armv6-m -mthumb -mfloat-abi=soft"
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linker_output_format = "elf32-littlearm"
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nop = "nop"
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io_regions = {0x4000_0000: 0x2000_0000,
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0xA000_0000: 0x6000_0000
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} # Origin, Length.
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@property
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def mem_map(self):
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return {
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"rom" : 0x0000_0000,
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"sram" : 0x2000_0000,
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"main_ram" : 0x1000_0000,
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"csr" : 0xA000_0000
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}
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def __init__(self, platform, variant, *args, **kwargs):
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super().__init__(*args, **kwargs)
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self.platform = platform
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self.reset = Signal()
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self.interrupt = Signal(2)
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pbus = wishbone.Interface(data_width=32, adr_width=30)
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self.periph_buses = [pbus]
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self.memory_buses = []
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def _mem_size(x):
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return log2_int(x // 512)
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self.cpu_params = dict(
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i_HCLK = ClockSignal("sys"),
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i_SYSRESETn = ~(ResetSignal() | self.reset),
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p_NUM_IRQ = len(self.interrupt),
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i_IRQ = self.interrupt,
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i_DBGRESETn = ~(ResetSignal() | self.reset),
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p_ITCM_SIZE = _mem_size(0 * 1024), # embedded ROM
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p_DTCM_SIZE = _mem_size(0 * 1024), # embedded RAM
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p_DEBUG_SEL = 1, # JTAG
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p_SMALL_DEBUG = True,
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i_CFGITCMEN = 0, # 1 = alias ITCM at 0x0
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o_DBGRESTARTED = Signal(),
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o_LOCKUP = Signal(),
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o_HALTED = Signal(),
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o_SYSRESETREQ = Signal(),
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i_NMI = 0,
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i_EDBGRQ = 0,
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i_DBGRESTART = 0,
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)
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def connect_axi(axi_bus, suffix=''):
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layout = axi_bus.layout_flat()
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dir_map = {DIR_M_TO_S: 'o', DIR_S_TO_M: 'i'}
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for group, signal, direction in layout:
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if signal in ['id', 'qos', 'first']:
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continue
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if signal == 'last':
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if group in ['b', 'a', 'ar', 'aw']:
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continue
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prefix = 'H' if signal == 'data' else ''
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direction = dir_map[direction]
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self.cpu_params[f'{direction}_{prefix}{group.upper()}{signal.upper()}{suffix}'] = \
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getattr(getattr(axi_bus, group), signal)
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pbus_axi = axi.AXIInterface(data_width=self.data_width, address_width=32)
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pbus_a2w = axi.AXI2Wishbone(pbus_axi, pbus, base_address=0)
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self.submodules += pbus_a2w
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connect_axi(pbus_axi)
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platform.add_source_dir("AT472-BU-98000-r0p1-00rel0/vivado/Arm_ipi_repository/CM1DbgAXI/logical/rtl")
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def connect_jtag(self, pads):
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self.cpu_params.update(
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i_SWDITMS = pads.tms,
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i_TDI = pads.tdi,
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o_TDO = pads.tdo,
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o_nTDOEN = Signal(),
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i_nTRST = pads.ntrst,
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i_SWCLKTCK = pads.tck,
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o_JTAGNSW = Signal(), # Indicates debug mode, JTAG or SWD
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o_JTAGTOP = Signal(), # ?
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o_SWDO = Signal(), # TODO
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o_SWDOEN = Signal(), # TODO
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)
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def do_finalize(self):
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self.specials += Instance("CortexM1DbgAXI", **self.cpu_params)
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@ -0,0 +1,137 @@
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#include <stdint.h>
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#include "system.h"
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#include "generated/soc.h"
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extern uint32_t _fdata_rom, _fdata, _edata, _fbss, _ebss, _fstack;
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extern void isr(void);
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void _start(void);
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void default_handler(void);
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void uart_handler_proxy(void);
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volatile unsigned int irqs_enabled;
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void _start(void) {
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__asm__(
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"mov r0, %0\n"
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"mov sp, r0\n" : : "r" (&_fstack)
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);
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uint32_t *y = &_fdata_rom;
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for (uint32_t *x = &_fdata; x < &_edata; x ++)
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*x = *y ++;
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for (uint32_t *x = &_fbss; x < &_ebss; x ++)
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*x = 0;
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__asm__("bl main");
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while(1);
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}
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void default_handler(void) {
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while(1);
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}
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void uart_handler_proxy(void) {
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NVIC->ISPR[0] = (1 << UART_INTERRUPT);
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isr();
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NVIC->ICPR[0] = (1 << UART_INTERRUPT);
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}
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const void* isr_vector[] __attribute__((__used__)) __attribute__((section(".isr_vector"))) = {
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&_fstack,
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_start, // reset
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default_handler, // nmi
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default_handler, // hard fault
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0, // reserved
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0, // reserved
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0, // reserved
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0, // reserved
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0, // reserved
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0, // reserved
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0, // reserved
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default_handler, // svc
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0, // reserved
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0, // reserved
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default_handler, // pend sv
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default_handler, // systick
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// external
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uart_handler_proxy,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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default_handler,
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};
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__asm__ (
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R"(
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.syntax unified
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.global __gnu_thumb1_case_uhi
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__gnu_thumb1_case_uhi:
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push {r0, r1}
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mov r1, lr
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lsrs r1, r1, #1
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lsls r0, r0, #1
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lsls r1, r1, #1
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ldrh r1, [r1, r0]
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lsls r1, r1, #1
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add lr, lr, r1
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pop {r0, r1}
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bx lr
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.global __gnu_thumb1_case_uqi
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__gnu_thumb1_case_uqi:
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mov r12, r1
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mov r1, lr
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lsrs r1, r1, #1
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lsls r1, r1, #1
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ldrb r1, [r1, r0]
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lsls r1, r1, #1
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add lr, lr, r1
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mov r1, r12
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bx lr
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.global __aeabi_uldivmod
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__aeabi_uldivmod:
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push {r0, r1}
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mov r0, sp
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push {r0, lr}
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ldr r0, [sp, #8]
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bl __udivmoddi4
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ldr r3, [sp, #4]
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mov lr, r3
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add sp, sp, #8
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pop {r2, r3}
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bx lr
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)"
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);
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@ -0,0 +1,52 @@
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#ifndef __IRQ_H
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#define __IRQ_H
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#include <stdint.h>
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#include "system.h"
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#include "generated/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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extern volatile unsigned int irqs_enabled;
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static inline unsigned int irq_getie(void)
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{
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return irqs_enabled; /* FIXME */
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}
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static inline void irq_setie(unsigned int ie)
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{
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if (ie)
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__asm__ volatile ("cpsie i" : : : "memory");
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else
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__asm__ volatile ("cpsid i" : : : "memory");
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irqs_enabled = ie;
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}
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static inline unsigned int irq_getmask(void)
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{
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return (1 << UART_INTERRUPT); // FIXME
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}
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static inline void irq_setmask(unsigned int mask)
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{
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// fixme: there are more interrupts
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NVIC->ISER[0] = mask;
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NVIC->ICER[0] = ~mask;
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}
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static inline unsigned int irq_pending(void)
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{
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// fixme: there are more interrupts
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return NVIC->ISPR[0];
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}
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#ifdef __cplusplus
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}
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#endif
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#endif /* __IRQ_H */
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@ -0,0 +1,39 @@
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#ifndef __SYSTEM_H
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#define __SYSTEM_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define UART_POLLING
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typedef struct
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{
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volatile uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
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uint32_t RESERVED0[31];
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volatile uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
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uint32_t RSERVED1[31];
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volatile uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
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uint32_t RESERVED2[31];
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volatile uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
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uint32_t RESERVED3[31];
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uint32_t RESERVED4[64];
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volatile uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
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} NVIC_Type;
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#define SCS_BASE (0xE000E000UL)
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#define NVIC_BASE (SCS_BASE + 0x0100UL)
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#define NVIC ((NVIC_Type *) NVIC_BASE)
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__attribute__((unused)) static void flush_cpu_icache(void){}; /* No instruction cache */
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__attribute__((unused)) static void flush_cpu_dcache(void){}; /* No instruction cache */
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void flush_l2_cache(void);
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void busy_wait(unsigned int ms);
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void busy_wait_us(unsigned int us);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __SYSTEM_H */
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