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Do not use super()
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parent
c44ff8941c
commit
51f4f920a2
2 changed files with 5 additions and 5 deletions
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@ -79,7 +79,7 @@ class _SimpleSelector(_Selector):
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(slot.state == SLOT_PENDING)
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))
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return Fragment(comb) + super().get_fragment()
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return Fragment(comb) + _Selector.get_fragment(self)
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class _FullSelector(_Selector):
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def get_fragment(self):
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@ -149,7 +149,7 @@ class _FullSelector(_Selector):
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select_stmt = If(has_mature, *best_mature).Else(select_stmt)
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comb.append(select_stmt)
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return Fragment(comb, sync) + super().get_fragment()
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return Fragment(comb, sync) + _Selector.get_fragment(self)
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class _Buffer:
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def __init__(self, source):
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@ -44,11 +44,11 @@ class _FrameInitiator(spi.SingleGenerator):
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("base", asmi_bits, 0, alignment_bits),
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("length", length_bits, 640*480*4, alignment_bits)
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]
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super().__init__(layout, spi.MODE_CONTINUOUS)
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spi.SingleGenerator.__init__(self, layout, spi.MODE_CONTINUOUS)
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class VTG(Actor):
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def __init__(self):
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super().__init__(
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Actor.__init__(self,
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("timing", Sink, [
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("hres", _hbits),
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("hsync_start", _hbits),
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@ -115,7 +115,7 @@ class VTG(Actor):
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class FIFO(Actor):
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def __init__(self):
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super().__init__(("dac", Sink, _dac_layout))
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Actor.__init__(self, ("dac", Sink, _dac_layout))
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self.vga_hsync_n = Signal()
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self.vga_vsync_n = Signal()
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