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soc/integration/soc_core: Fix with_uartbone changes.
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@ -256,7 +256,7 @@ class SoCCore(LiteXSoC):
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# Add UARTBone.
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if with_uartbone:
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self.add_uartbone(baudrate=uart_baudrate, fifo_depth=uart_fifo_depth, with_dynamic_baudrate=with_dynamic_baudrate)
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self.add_uartbone(baudrate=uart_baudrate, with_dynamic_baudrate=uart_with_dynamic_baudrate)
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# Add UART.
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if with_uart:
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