soc/interconnect: add wishbonebridge and uart bridge
This commit is contained in:
Florent Kermarrec
parent
89b189ce4a
commit
525da89c7d
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from migen import *
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from litex.soc.interconnect.wishbonebridge import WishboneStreamingBridge
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from litex.soc.cores.uart.core import RS232PHY
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class UARTWishboneBridge(WishboneStreamingBridge):
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def __init__(self, pads, clk_freq, baudrate=115200):
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self.submodules.phy = RS232PHY(pads, clk_freq, baudrate)
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WishboneStreamingBridge.__init__(self, self.phy, clk_freq)
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from migen import *
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from migen.genlib.misc import chooser, WaitTimer
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from migen.genlib.record import Record
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from migen.genlib.fsm import FSM, NextState
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.stream import Sink, Source
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@ResetInserter()
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@CEInserter()
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class Counter(Module):
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def __init__(self, *args, increment=1, **kwargs):
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self.value = Signal(*args, **kwargs)
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self.width = flen(self.value)
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self.sync += self.value.eq(self.value+increment)
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class WishboneStreamingBridge(Module):
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cmds = {
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"write": 0x01,
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"read": 0x02
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}
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def __init__(self, phy, clk_freq):
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self.wishbone = wishbone.Interface()
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# # #
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byte_counter = Counter(3)
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word_counter = Counter(8)
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self.submodules += byte_counter, word_counter
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cmd = Signal(8)
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cmd_ce = Signal()
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length = Signal(8)
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length_ce = Signal()
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address = Signal(32)
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address_ce = Signal()
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data = Signal(32)
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rx_data_ce = Signal()
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tx_data_ce = Signal()
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self.sync += [
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If(cmd_ce, cmd.eq(phy.source.data)),
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If(length_ce, length.eq(phy.source.data)),
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If(address_ce, address.eq(Cat(phy.source.data, address[0:24]))),
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If(rx_data_ce,
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data.eq(Cat(phy.source.data, data[0:24]))
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).Elif(tx_data_ce,
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data.eq(self.wishbone.dat_r)
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)
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]
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fsm = InsertReset(FSM(reset_state="IDLE"))
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timer = WaitTimer(clk_freq//10)
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self.submodules += fsm, timer
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self.comb += [
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fsm.reset.eq(timer.done),
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phy.source.ack.eq(1)
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]
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fsm.act("IDLE",
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If(phy.source.stb,
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cmd_ce.eq(1),
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If((phy.source.data == self.cmds["write"]) |
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(phy.source.data == self.cmds["read"]),
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NextState("RECEIVE_LENGTH")
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),
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byte_counter.reset.eq(1),
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word_counter.reset.eq(1)
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)
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)
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fsm.act("RECEIVE_LENGTH",
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If(phy.source.stb,
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length_ce.eq(1),
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NextState("RECEIVE_ADDRESS")
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)
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)
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fsm.act("RECEIVE_ADDRESS",
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If(phy.source.stb,
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address_ce.eq(1),
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byte_counter.ce.eq(1),
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If(byte_counter.value == 3,
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If(cmd == self.cmds["write"],
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NextState("RECEIVE_DATA")
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).Elif(cmd == self.cmds["read"],
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NextState("READ_DATA")
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),
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byte_counter.reset.eq(1),
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)
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)
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)
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fsm.act("RECEIVE_DATA",
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If(phy.source.stb,
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rx_data_ce.eq(1),
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byte_counter.ce.eq(1),
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If(byte_counter.value == 3,
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NextState("WRITE_DATA"),
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byte_counter.reset.eq(1)
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)
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)
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)
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self.comb += [
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self.wishbone.adr.eq(address + word_counter.value),
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self.wishbone.dat_w.eq(data),
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self.wishbone.sel.eq(2**flen(self.wishbone.sel)-1)
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]
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fsm.act("WRITE_DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(1),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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word_counter.ce.eq(1),
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If(word_counter.value == (length-1),
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NextState("IDLE")
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).Else(
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NextState("RECEIVE_DATA")
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)
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)
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)
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fsm.act("READ_DATA",
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self.wishbone.stb.eq(1),
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self.wishbone.we.eq(0),
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self.wishbone.cyc.eq(1),
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If(self.wishbone.ack,
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tx_data_ce.eq(1),
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NextState("SEND_DATA")
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)
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)
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self.comb += \
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chooser(data, byte_counter.value, phy.sink.data, n=4, reverse=True)
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fsm.act("SEND_DATA",
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phy.sink.stb.eq(1),
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If(phy.sink.ack,
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byte_counter.ce.eq(1),
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If(byte_counter.value == 3,
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word_counter.ce.eq(1),
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If(word_counter.value == (length-1),
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NextState("IDLE")
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).Else(
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NextState("READ_DATA"),
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byte_counter.reset.eq(1)
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)
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)
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)
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)
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self.comb += timer.wait.eq(~fsm.ongoing("IDLE"))
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if phy.sink.description.packetized:
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self.comb += [
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phy.sink.sop.eq((byte_counter.value == 0) & (word_counter.value == 0)),
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phy.sink.eop.eq((byte_counter.value == 3) & (word_counter.value == (length-1)))
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]
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if hasattr(phy.sink, "length"):
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self.comb += phy.sink.length.eq(4*length)
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