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tools/litex_sim: update copyrights and cosmetic changes

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Florent Kermarrec 2020-01-24 13:58:49 +01:00
parent b280bb2ff2
commit 52765488b5
1 changed files with 39 additions and 35 deletions
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74
litex/tools/litex_sim.py
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@ -1,6 +1,7 @@
#!/usr/bin/env python3 #!/usr/bin/env python3
# This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr> # This file is Copyright (c) 2015-2020 Florent Kermarrec <florent@enjoy-digital.fr>
# This file is Copyright (c) 2020 Piotr Binkowski <pbinkowski@antmicro.com>
# This file is Copyright (c) 2017 Pierre-Olivier Vauboin <po@lambdaconcept> # This file is Copyright (c) 2017 Pierre-Olivier Vauboin <po@lambdaconcept>
# License: BSD # License: BSD
@ -65,38 +66,38 @@ class Platform(SimPlatform):
# DFI PHY model settings --------------------------------------------------------------------------- # DFI PHY model settings ---------------------------------------------------------------------------
sdram_module_nphases = { sdram_module_nphases = {
"SDR": 1, "SDR": 1,
"DDR": 2, "DDR": 2,
"LPDDR": 2, "LPDDR": 2,
"DDR2": 2, "DDR2": 2,
"DDR3": 4, "DDR3": 4,
} }
def get_sdram_phy_settings(memtype, data_width, clk_freq): def get_sdram_phy_settings(memtype, data_width, clk_freq):
nphases = sdram_module_nphases[memtype] nphases = sdram_module_nphases[memtype]
# Default litex_sim settings
if memtype == "SDR": if memtype == "SDR":
rdphase = 0 # Settings from gensdrphy
wrphase = 0 rdphase = 0
rdcmdphase = 0 wrphase = 0
wrcmdphase = 0 rdcmdphase = 0
cl = 2 wrcmdphase = 0
cwl = None cl = 2
read_latency = 4 cwl = None
write_latency = 0 read_latency = 4
# Settings taken from s6ddrphy write_latency = 0
elif memtype in ["DDR", "LPDDR"]: elif memtype in ["DDR", "LPDDR"]:
rdphase = 0 # Settings from s6ddrphy
wrphase = 1 rdphase = 0
rdcmdphase = 1 wrphase = 1
wrcmdphase = 0 rdcmdphase = 1
cl = 3 wrcmdphase = 0
cwl = None cl = 3
read_latency = 5 cwl = None
write_latency = 0 read_latency = 5
# Settings taken from s7ddrphy write_latency = 0
elif memtype in ["DDR2", "DDR3"]: elif memtype in ["DDR2", "DDR3"]:
# Settings from s7ddrphy
tck = 2/(2*nphases*clk_freq) tck = 2/(2*nphases*clk_freq)
cmd_latency = 0 cmd_latency = 0
cl, cwl = get_cl_cw(memtype, tck) cl, cwl = get_cl_cw(memtype, tck)
@ -109,21 +110,21 @@ def get_sdram_phy_settings(memtype, data_width, clk_freq):
write_latency = cwl_sys_latency write_latency = cwl_sys_latency
sdram_phy_settings = { sdram_phy_settings = {
"nphases": nphases, "nphases": nphases,
"rdphase": rdphase, "rdphase": rdphase,
"wrphase": wrphase, "wrphase": wrphase,
"rdcmdphase": rdcmdphase, "rdcmdphase": rdcmdphase,
"wrcmdphase": wrcmdphase, "wrcmdphase": wrcmdphase,
"cl": cl, "cl": cl,
"cwl": cwl, "cwl": cwl,
"read_latency": read_latency, "read_latency": read_latency,
"write_latency": write_latency, "write_latency": write_latency,
} }
return PhySettings( return PhySettings(
memtype = memtype, memtype = memtype,
databits = data_width, databits = data_width,
dfi_databits = data_width if memtype == "SDR" else 2*data_width, dfi_databits = data_width if memtype == "SDR" else 2*data_width,
**sdram_phy_settings, **sdram_phy_settings,
) )
@ -168,7 +169,10 @@ class SimSoC(SoCSDRAM):
sdram_module_cls = getattr(litedram_modules, sdram_module) sdram_module_cls = getattr(litedram_modules, sdram_module)
sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype]) sdram_rate = "1:{}".format(sdram_module_nphases[sdram_module_cls.memtype])
sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate) sdram_module = sdram_module_cls(sdram_clk_freq, sdram_rate)
phy_settings = get_sdram_phy_settings(sdram_module.memtype, sdram_data_width, sdram_clk_freq) phy_settings = get_sdram_phy_settings(
memtype = sdram_module.memtype,
data_width = sdram_data_width,
clk_freq = sdram_clk_freq)
self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings) self.submodules.sdrphy = SDRAMPHYModel(sdram_module, phy_settings)
self.register_sdram( self.register_sdram(
self.sdrphy, self.sdrphy,