targets: remove USBSoC from minispartan6 (example available here: https://github.com/enjoy-digital/scarab-soc)
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@ -9,11 +9,6 @@ from misoclib.mem.sdram.phy import gensdrphy
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from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
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from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
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from misoclib.soc.sdram import SDRAMSoC
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from misoclib.soc.sdram import SDRAMSoC
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from misoclib.com.liteusb.common import *
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from misoclib.com.liteusb.phy.ft245 import FT245PHY
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from misoclib.com.liteusb.core import LiteUSBCore
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from misoclib.com.liteusb.frontend.uart import LiteUSBUART
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class _CRG(Module):
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class _CRG(Module):
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def __init__(self, platform, clk_freq):
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def __init__(self, platform, clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_sys = ClockDomain()
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@ -82,36 +77,4 @@ class BaseSoC(SDRAMSoC):
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AS4C16M16(clk_freq))
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AS4C16M16(clk_freq))
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self.register_sdram_phy(self.sdrphy)
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self.register_sdram_phy(self.sdrphy)
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class USBSoC(BaseSoC):
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csr_map = {
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"usb_dma": 16,
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}
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csr_map.update(BaseSoC.csr_map)
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usb_map = {
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"uart": 0,
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"dma": 1
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}
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def __init__(self, platform, **kwargs):
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BaseSoC.__init__(self, platform, with_uart=False, **kwargs)
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self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq)
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self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False)
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# UART
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usb_uart_port = self.usb_core.crossbar.get_port(self.usb_map["uart"])
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self.submodules.uart = LiteUSBUART(usb_uart_port)
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# DMA
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usb_dma_port = self.usb_core.crossbar.get_port(self.usb_map["dma"])
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usb_dma_loopback_fifo = SyncFIFO(user_description(8), 1024, buffered=True)
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self.submodules += usb_dma_loopback_fifo
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self.comb += [
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usb_dma_port.source.connect(usb_dma_loopback_fifo.sink),
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usb_dma_loopback_fifo.source.connect(usb_dma_port.sink)
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]
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default_subtarget = BaseSoC
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default_subtarget = BaseSoC
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