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targets: remove USBSoC from minispartan6 (example available here: https://github.com/enjoy-digital/scarab-soc)

This commit is contained in:
Florent Kermarrec 2015-09-07 12:46:37 +02:00
parent 8e8cc8e5a6
commit 5301a1776d
1 changed files with 0 additions and 37 deletions
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37
targets/minispartan6.py
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@ -9,11 +9,6 @@ from misoclib.mem.sdram.phy import gensdrphy
from misoclib.mem.sdram.core.lasmicon import LASMIconSettings
from misoclib.soc.sdram import SDRAMSoC
from misoclib.com.liteusb.common import *
from misoclib.com.liteusb.phy.ft245 import FT245PHY
from misoclib.com.liteusb.core import LiteUSBCore
from misoclib.com.liteusb.frontend.uart import LiteUSBUART
class _CRG(Module):
def __init__(self, platform, clk_freq):
self.clock_domains.cd_sys = ClockDomain()
@ -82,36 +77,4 @@ class BaseSoC(SDRAMSoC):
AS4C16M16(clk_freq))
self.register_sdram_phy(self.sdrphy)
class USBSoC(BaseSoC):
csr_map = {
"usb_dma": 16,
}
csr_map.update(BaseSoC.csr_map)
usb_map = {
"uart": 0,
"dma": 1
}
def __init__(self, platform, **kwargs):
BaseSoC.__init__(self, platform, with_uart=False, **kwargs)
self.submodules.usb_phy = FT245PHY(platform.request("usb_fifo"), self.clk_freq)
self.submodules.usb_core = LiteUSBCore(self.usb_phy, self.clk_freq, with_crc=False)
# UART
usb_uart_port = self.usb_core.crossbar.get_port(self.usb_map["uart"])
self.submodules.uart = LiteUSBUART(usb_uart_port)
# DMA
usb_dma_port = self.usb_core.crossbar.get_port(self.usb_map["dma"])
usb_dma_loopback_fifo = SyncFIFO(user_description(8), 1024, buffered=True)
self.submodules += usb_dma_loopback_fifo
self.comb += [
usb_dma_port.source.connect(usb_dma_loopback_fifo.sink),
usb_dma_loopback_fifo.source.connect(usb_dma_port.sink)
]
default_subtarget = BaseSoC