build/altera: Fix IP integration

2022-12-23 16:51:35 +01:00 · 2022-12-23 16:51:35 +01:00 · 5307b5e3f2
parent 5dd1bb5fdb
commit 5307b5e3f2
1 changed files with 2 additions and 3 deletions
--- a/litex/build/altera/quartus.py
+++ b/litex/build/altera/quartus.py
@ -138,10 +138,9 @@ class AlteraQuartusToolchain(GenericToolchain):
                    if fpath not in platform.verilog_include_paths:
                        platform.verilog_include_paths.append(fpath)

-        # Add ips
+        # Add IPs
        for filename in self.platform.ips:
-            tpl = "set_global_assignment -name QSYS_FILE {filename}"
-            qsf.append(tpl.replace(filename=filename.replace("\\", "/")))
+            qsf.append("set_global_assignment -name QSYS_FILE " + filename.replace("\\", "/"))

        # Add include paths
        for path in self.platform.verilog_include_paths: