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build/altera: Fix IP integration

This commit is contained in:
stone3311 2022-12-23 16:51:35 +01:00
parent 5dd1bb5fdb
commit 5307b5e3f2
1 changed files with 2 additions and 3 deletions
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5
litex/build/altera/quartus.py
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@ -138,10 +138,9 @@ class AlteraQuartusToolchain(GenericToolchain):
if fpath not in platform.verilog_include_paths: if fpath not in platform.verilog_include_paths:
platform.verilog_include_paths.append(fpath) platform.verilog_include_paths.append(fpath)
# Add ips # Add IPs
for filename in self.platform.ips: for filename in self.platform.ips:
tpl = "set_global_assignment -name QSYS_FILE {filename}" qsf.append("set_global_assignment -name QSYS_FILE " + filename.replace("\\", "/"))
qsf.append(tpl.replace(filename=filename.replace("\\", "/")))
# Add include paths # Add include paths
for path in self.platform.verilog_include_paths: for path in self.platform.verilog_include_paths: