soc: create specific add_jtagbone method instead of integrating it in add_uartbnone.

Creates a JTAG bridge in the SoC simply with self.add_jtagbone(), almost comes for free :)

litex/soc/integration/soc.py

@@ -1169,15 +1169,18 @@ class LiteXSoC(SoC):
         from litex.soc.cores import uart
         if clk_freq is None:
             clk_freq = self.sys_clk_freq
-        if name == "jtag_uart":
-            from litex.soc.cores.jtag import JTAGPHY
-            phy = JTAGPHY(device=self.platform.device)
-        else:
-            phy = uart.UARTPHY(self.platform.request(name), clk_freq, baudrate)
-        self.submodules += phy
-        self.submodules.uartbone = uart.UARTBone(phy=phy, clk_freq=clk_freq, cd=cd)
+        self.submodules.phy = uart.UARTPHY(self.platform.request(name), clk_freq, baudrate)
+        self.submodules.uartbone = uart.UARTBone(phy=self.phy, clk_freq=clk_freq, cd=cd)
         self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
 
+    # Add JTAGbone ---------------------------------------------------------------------------------
+    def add_jtagbone(self):
+        from litex.soc.cores import uart
+        from litex.soc.cores.jtag import JTAGPHY
+        self.submodules.phy = JTAGPHY(device=self.platform.device)
+        self.submodules.jtagbone = uart.UARTBone(phy=self.phy, clk_freq=self.sys_clk_freq)
+        self.bus.add_master(name="jtagbone", master=self.jtagbone.wishbone)
+
     # Add SDRAM ------------------------------------------------------------------------------------
     def add_sdram(self, name, phy, module, origin, size=None, with_bist=False, with_soc_interconnect=True,
         l2_cache_size           = 8192,