Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

boards/arty : Add directly connected spi clk pin to avoid need for STARTUPE2

This commit is contained in:
Tom Keddie 2019-06-10 08:33:02 -07:00
parent 3a72688b28
commit 5346c3684f
1 changed files with 4 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
litex/boards/platforms/arty.py
View File

@ -79,13 +79,15 @@ _io = [
IOStandard("LVCMOS33"),
),
("spiflash4x", 0, # clock needs to be accessed through STARTUPE2
("spiflash4x", 0,
Subsignal("cs_n", Pins("L13")),
Subsignal("clk", Pins("L16")),
Subsignal("dq", Pins("K17", "K18", "L14", "M14")),
IOStandard("LVCMOS33")
),
("spiflash", 0, # clock needs to be accessed through STARTUPE2
("spiflash", 0,
Subsignal("cs_n", Pins("L13")),
Subsignal("clk", Pins("L16")),
Subsignal("mosi", Pins("K17")),
Subsignal("miso", Pins("K18")),
Subsignal("wp", Pins("L14")),