First video mixing working (hacky)
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e35315bb24
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@ -136,7 +136,7 @@ class FrameExtraction(Module):
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vsync_r.eq(self.vsync)
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]
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fifo = AsyncFIFO(layout_len(frame_layout), 256)
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fifo = AsyncFIFO(layout_len(frame_layout), 512)
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self.add_submodule(fifo, {"write": "pix", "read": "sys"})
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self.comb += [
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fifo.we.eq(fifo_stb),
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@ -129,7 +129,7 @@ class FIFO(Module):
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###
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data_width = 2+2*3*bpc_dac
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fifo = AsyncFIFO(data_width, 256)
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fifo = AsyncFIFO(data_width, 512)
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self.add_submodule(fifo, {"write": "sys", "read": "vga"})
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fifo_in = self.dac.payload
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fifo_out = Record(dac_layout)
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10
top.py
10
top.py
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@ -13,7 +13,7 @@ from cif import get_macros
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version = get_macros("common/version.h")["VERSION"][1:-1]
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clk_freq = (83 + Fraction(1, 3))*1000000
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clk_freq = (62 + Fraction(1, 2))*1000000
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sram_size = 4096 # in bytes
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l2_size = 8192 # in bytes
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@ -93,10 +93,10 @@ class SoC(Module):
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#
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self.submodules.asmicon = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
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asmiport_wb = self.asmicon.hub.get_port()
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asmiport_fb0 = self.asmicon.hub.get_port(2)
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asmiport_fb1 = self.asmicon.hub.get_port(2)
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asmiport_dvi0 = self.asmicon.hub.get_port(2)
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asmiport_dvi1 = self.asmicon.hub.get_port(2)
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asmiport_fb0 = self.asmicon.hub.get_port(4)
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asmiport_fb1 = self.asmicon.hub.get_port(4)
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asmiport_dvi0 = self.asmicon.hub.get_port(4)
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asmiport_dvi1 = self.asmicon.hub.get_port(4)
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self.asmicon.finalize()
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#
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