First video mixing working (hacky)

This commit is contained in:
Sebastien Bourdeauducq 2013-05-12 15:58:08 +02:00
parent e35315bb24
commit 534dec62eb
3 changed files with 7 additions and 7 deletions

View File

@ -136,7 +136,7 @@ class FrameExtraction(Module):
vsync_r.eq(self.vsync)
]
fifo = AsyncFIFO(layout_len(frame_layout), 256)
fifo = AsyncFIFO(layout_len(frame_layout), 512)
self.add_submodule(fifo, {"write": "pix", "read": "sys"})
self.comb += [
fifo.we.eq(fifo_stb),

View File

@ -129,7 +129,7 @@ class FIFO(Module):
###
data_width = 2+2*3*bpc_dac
fifo = AsyncFIFO(data_width, 256)
fifo = AsyncFIFO(data_width, 512)
self.add_submodule(fifo, {"write": "sys", "read": "vga"})
fifo_in = self.dac.payload
fifo_out = Record(dac_layout)

10
top.py
View File

@ -13,7 +13,7 @@ from cif import get_macros
version = get_macros("common/version.h")["VERSION"][1:-1]
clk_freq = (83 + Fraction(1, 3))*1000000
clk_freq = (62 + Fraction(1, 2))*1000000
sram_size = 4096 # in bytes
l2_size = 8192 # in bytes
@ -93,10 +93,10 @@ class SoC(Module):
#
self.submodules.asmicon = asmicon.ASMIcon(sdram_phy, sdram_geom, sdram_timing)
asmiport_wb = self.asmicon.hub.get_port()
asmiport_fb0 = self.asmicon.hub.get_port(2)
asmiport_fb1 = self.asmicon.hub.get_port(2)
asmiport_dvi0 = self.asmicon.hub.get_port(2)
asmiport_dvi1 = self.asmicon.hub.get_port(2)
asmiport_fb0 = self.asmicon.hub.get_port(4)
asmiport_fb1 = self.asmicon.hub.get_port(4)
asmiport_dvi0 = self.asmicon.hub.get_port(4)
asmiport_dvi1 = self.asmicon.hub.get_port(4)
self.asmicon.finalize()
#