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Merge pull request #425 from esden/csr-cod-split-reg 

Make CSR documentation diagrams, with more than 8 bits, be split into multiple lanes.
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Sean Cross 2020-03-14 18:08:24 +08:00 committed by GitHub
parent c0f067c3cf 57576fa8fc
commit 536ae0e619
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GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 11 additions and 1 deletions
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12
litex/soc/doc/csr.py
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@ -235,7 +235,9 @@ class DocumentedCSRRegion:
print("", file=stream) print("", file=stream)
print(" {", file=stream) print(" {", file=stream)
print(" \"reg\": [", file=stream) print(" \"reg\": [", file=stream)
multilane = False
if len(reg.fields) > 0: if len(reg.fields) > 0:
min_field_size = self.csr_data_width
bit_offset = 0 bit_offset = 0
for field in reg.fields: for field in reg.fields:
field_name = field.name field_name = field.name
@ -254,6 +256,9 @@ class DocumentedCSRRegion:
term="" term=""
print(" {\"name\": \"" + field_name + "\", " + type_str + attr_str + "\"bits\": " + str(field.size) + "}" + term, file=stream) print(" {\"name\": \"" + field_name + "\", " + type_str + attr_str + "\"bits\": " + str(field.size) + "}" + term, file=stream)
bit_offset = field.offset + field.size bit_offset = field.offset + field.size
min_field_size = min(min_field_size, field.size)
if min_field_size < 8:
multilane = True
if bit_offset != self.busword: if bit_offset != self.busword:
print(" {\"bits\": " + str(self.busword - bit_offset) + "}", file=stream) print(" {\"bits\": " + str(self.busword - bit_offset) + "}", file=stream)
else: else:
@ -265,8 +270,13 @@ class DocumentedCSRRegion:
attr_str = "\"attr\": 'reset: " + str(reg.reset_value) + "', " attr_str = "\"attr\": 'reset: " + str(reg.reset_value) + "', "
print(" {\"name\": \"" + reg.short_name.lower() + self.bit_range(reg.offset, reg.offset + reg.size, empty_if_zero=True) + "\", " + attr_str + "\"bits\": " + str(reg.size) + "}" + term, file=stream) print(" {\"name\": \"" + reg.short_name.lower() + self.bit_range(reg.offset, reg.offset + reg.size, empty_if_zero=True) + "\", " + attr_str + "\"bits\": " + str(reg.size) + "}" + term, file=stream)
if reg.size != self.csr_data_width: if reg.size != self.csr_data_width:
multilane = True
print(" {\"bits\": " + str(self.csr_data_width - reg.size) + "},", file=stream) print(" {\"bits\": " + str(self.csr_data_width - reg.size) + "},", file=stream)
print(" ], \"config\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": 1 }, \"options\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": 1}", file=stream) if multilane:
lanes = self.busword / 8
else:
lanes = 1
print(" ], \"config\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": " + str(lanes) + " }, \"options\": {\"hspace\": 400, \"bits\": " + str(self.busword) + ", \"lanes\": " + str(lanes) + "}", file=stream)
print(" }", file=stream) print(" }", file=stream)
print("", file=stream) print("", file=stream)