boards: always define timing constraints the same way (1e9/freq_mhz)

litex/boards/platforms/genesys2.py

@@ -118,6 +118,6 @@ class Platform(XilinxPlatform):
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
         except ConstraintError:
             pass

litex/boards/platforms/kc705.py

@@ -553,15 +553,15 @@ set_property CONFIG_VOLTAGE 2.5 [current_design]
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
         try:
-            self.add_period_constraint(self.lookup_request("clk200").p, 5.0)
+            self.add_period_constraint(self.lookup_request("clk200").p, 1e9/200e6)
         except ConstraintError:
             pass
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
         except ConstraintError:
             pass
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks").tx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks").tx, 1e9/125e6)
         except ConstraintError:
             pass
         if isinstance(self.toolchain, XilinxISEToolchain):

litex/boards/platforms/nexys_video.py

@@ -239,6 +239,6 @@ class Platform(XilinxPlatform):
     def do_finalize(self, fragment):
         XilinxPlatform.do_finalize(self, fragment)
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks").rx, 1e9/125e6)
         except ConstraintError:
             pass

litex/boards/platforms/versa_ecp3.py

@@ -85,11 +85,11 @@ class Platform(LatticePlatform):
     def do_finalize(self, fragment):
         LatticePlatform.do_finalize(self, fragment)
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
         except ConstraintError:
             pass
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6)
         except ConstraintError:
             pass
 

litex/boards/platforms/versa_ecp5.py

@@ -184,11 +184,11 @@ class Platform(LatticePlatform):
 
     def do_finalize(self, fragment):
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks", 0).rx, 1e9/125e6)
         except ConstraintError:
             pass
         try:
-            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 8.0)
+            self.add_period_constraint(self.lookup_request("eth_clocks", 1).rx, 1e9/125e6)
         except ConstraintError:
             pass
 

litex/boards/targets/arty.py

@@ -104,8 +104,8 @@ class EthernetSoC(BaseSoC):
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 80.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 80.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6)
         self.platform.add_false_path_constraints(
             self.crg.cd_sys.clk,
             self.ethphy.crg.cd_eth_rx.clk,

litex/boards/targets/genesys2.py

@@ -95,8 +95,8 @@ class EthernetSoC(BaseSoC):
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
         self.platform.add_false_path_constraints(
             self.crg.cd_sys.clk,
             self.ethphy.crg.cd_eth_rx.clk,

litex/boards/targets/kc705.py

@@ -95,8 +95,8 @@ class EthernetSoC(BaseSoC):
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
         self.platform.add_false_path_constraints(
             self.crg.cd_sys.clk,
             self.ethphy.crg.cd_eth_rx.clk,

litex/boards/targets/nexys_video.py

@@ -101,8 +101,8 @@ class EthernetSoC(BaseSoC):
 
         self.ethphy.crg.cd_eth_rx.clk.attr.add("keep")
         self.ethphy.crg.cd_eth_tx.clk.attr.add("keep")
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 8.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6)
-        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 8.0)
+        self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6)
         self.platform.add_false_path_constraints(
             self.crg.cd_sys.clk,
             self.ethphy.crg.cd_eth_rx.clk,

litex/boards/targets/versa_ecp5.py

@@ -41,7 +41,7 @@ class _CRG(Module):
         # clk / rst
         clk100 = platform.request("clk100")
         rst_n = platform.request("rst_n")
-        platform.add_period_constraint(clk100, 10.0)
+        platform.add_period_constraint(clk100, 1e9/100e6)
 
         # power on reset
         por_count = Signal(16, reset=2**16-1)