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build: only add UCF constraints for the cores that are present
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parent
26c0261a4e
commit
53e5c4f59c
1 changed files with 17 additions and 6 deletions
23
build.py
23
build.py
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@ -15,35 +15,46 @@ def main():
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platform.add_platform_command("""
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platform.add_platform_command("""
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NET "{clk50}" TNM_NET = "GRPclk50";
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NET "{clk50}" TNM_NET = "GRPclk50";
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TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
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TIMESPEC "TSclk50" = PERIOD "GRPclk50" 20 ns HIGH 50%;
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""", clk50=platform.lookup_request("clk50"))
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platform.add_platform_command("""
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INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
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INST "m1crg/wr_bufpll" LOC = "BUFPLL_X0Y2";
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INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
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INST "m1crg/rd_bufpll" LOC = "BUFPLL_X0Y3";
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PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
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PIN "m1crg/bufg_x1.O" CLOCK_DEDICATED_ROUTE = FALSE;
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""")
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if hasattr(soc, "fb"):
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platform.add_platform_command("""
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NET "vga_clk" TNM_NET = "GRPvga_clk";
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NET "vga_clk" TNM_NET = "GRPvga_clk";
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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NET "sys_clk" TNM_NET = "GRPsys_clk";
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TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSise_sucks1" = FROM "GRPvga_clk" TO "GRPsys_clk" TIG;
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TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
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TIMESPEC "TSise_sucks2" = FROM "GRPsys_clk" TO "GRPvga_clk" TIG;
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""")
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if hasattr(soc, "minimac"):
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platform.add_platform_command("""
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NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
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NET "{phy_rx_clk}" TNM_NET = "GRPphy_rx_clk";
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NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
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NET "{phy_tx_clk}" TNM_NET = "GRPphy_tx_clk";
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TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
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TIMESPEC "TSphy_rx_clk" = PERIOD "GRPphy_rx_clk" 40 ns HIGH 50%;
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TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
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TIMESPEC "TSphy_tx_clk" = PERIOD "GRPphy_tx_clk" 40 ns HIGH 50%;
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TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
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TIMESPEC "TSphy_tx_clk_io" = FROM "GRPphy_tx_clk" TO "PADS" 10 ns;
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TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
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TIMESPEC "TSphy_rx_clk_io" = FROM "PADS" TO "GRPphy_rx_clk" 10 ns;
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""",
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phy_rx_clk=platform.lookup_request("eth_clocks").rx,
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phy_tx_clk=platform.lookup_request("eth_clocks").tx,)
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if hasattr(soc, "dvisampler0"):
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platform.add_platform_command("""
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NET "{dviclk0}" TNM_NET = "GRPdviclk0";
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NET "{dviclk0}" TNM_NET = "GRPdviclk0";
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NET "{dviclk0}" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "{dviclk0}" CLOCK_DEDICATED_ROUTE = FALSE;
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TIMESPEC "TSdviclk0" = PERIOD "GRPdviclk0" 26.7 ns HIGH 50%;
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TIMESPEC "TSdviclk0" = PERIOD "GRPdviclk0" 26.7 ns HIGH 50%;
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""", dviclk0=platform.lookup_request("dvi_in", 0).clk)
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platform.add_platform_command("""
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NET "{dviclk1}" TNM_NET = "GRPdviclk1";
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NET "{dviclk1}" TNM_NET = "GRPdviclk1";
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NET "{dviclk1}" CLOCK_DEDICATED_ROUTE = FALSE;
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NET "{dviclk1}" CLOCK_DEDICATED_ROUTE = FALSE;
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TIMESPEC "TSdviclk1" = PERIOD "GRPdviclk1" 26.7 ns HIGH 50%;
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TIMESPEC "TSdviclk1" = PERIOD "GRPdviclk1" 26.7 ns HIGH 50%;
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""",
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""", dviclk1=platform.lookup_request("dvi_in", 1).clk)
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clk50=platform.lookup_request("clk50"),
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phy_rx_clk=platform.lookup_request("eth_clocks").rx,
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phy_tx_clk=platform.lookup_request("eth_clocks").tx,
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dviclk0=platform.lookup_request("dvi_in", 0).clk,
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dviclk1=platform.lookup_request("dvi_in", 1).clk)
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for d in ["m1crg", "s6ddrphy", "minimac3"]:
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for d in ["m1crg", "s6ddrphy", "minimac3"]:
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platform.add_source_dir(os.path.join("verilog", d))
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platform.add_source_dir(os.path.join("verilog", d))
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