Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

bank/description/Register: add get_size

Browse source
This commit is contained in:
Sebastien Bourdeauducq 2013-03-25 14:43:44 +01:00
parent 3da98ea04d
commit 53edc3557e
1 changed files with 6 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
migen/bank/description.py
View file

@ -19,6 +19,9 @@ class RegisterRaw(_Register):
self.r = Signal(self.size) self.r = Signal(self.size)
self.w = Signal(self.size) self.w = Signal(self.size)
def get_size(self):
return self.size
(READ_ONLY, WRITE_ONLY, READ_WRITE) = range(3) (READ_ONLY, WRITE_ONLY, READ_WRITE) = range(3)
class Field: class Field:
@ -45,6 +48,9 @@ class RegisterFields(_Register):
_Register.__init__(self, name) _Register.__init__(self, name)
self.fields = fields self.fields = fields
def get_size(self):
return sum(field.size for field in self.fields)
class RegisterField(RegisterFields): class RegisterField(RegisterFields):
def __init__(self, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False, name=None): def __init__(self, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0, atomic_write=False, name=None):
self.field = Field(size, access_bus, access_dev, reset, atomic_write, name="") self.field = Field(size, access_bus, access_dev, reset, atomic_write, name="")