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cpu/femtorv: Rewrite FemtoRV Mem Bus to Wishbone adaption (thanks @BrunoLevy for the FemtoRV bus clarifications). 

Fixes the SDRAM accesses :)
This commit is contained in:
Florent Kermarrec 2021-11-19 15:43:15 +01:00
parent 605b6aff7c
commit 54a4e6c1f6
1 changed files with 34 additions and 32 deletions
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66
litex/soc/cores/cpu/femtorv/core.py
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@ -82,53 +82,55 @@ class FemtoRV(CPU):
# Adapt FemtoRV Mem Bus to Wishbone. # Adapt FemtoRV Mem Bus to Wishbone.
# ---------------------------------- # ----------------------------------
# Bytes to Words addressing conversion.
self.comb += idbus.adr.eq(mbus.addr[2:])
# Wdata/WMask direct connection.
self.comb += idbus.dat_w.eq(mbus.wdata)
self.comb += idbus.sel.eq(mbus.wmask)
# Control adaptation.
latch = Signal() latch = Signal()
write = mbus.wmask != 0 write = mbus.wmask != 0
read = mbus.rstrb read = mbus.rstrb
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="WAIT")
fsm.act("IDLE", fsm.act("WAIT",
idbus.stb.eq(read | write), # Latch Address + Bytes to Words conversion.
idbus.cyc.eq(read | write), NextValue(idbus.adr, mbus.addr[2:]),
idbus.we.eq(write),
If(read, # Latch Wdata/WMask.
mbus.rbusy.eq(1), NextValue(idbus.dat_w, mbus.wdata),
NextState("READ") NextValue(idbus.sel, mbus.wmask),
).Elif(write,
mbus.wbusy.eq(1), # If Read or Write, jump to access.
NextState("WRITE") If(read | write,
NextValue(idbus.we, write),
NextState("WB-ACCESS")
) )
) )
fsm.act("READ", fsm.act("WB-ACCESS",
idbus.stb.eq(1), idbus.stb.eq(1),
idbus.cyc.eq(1), idbus.cyc.eq(1),
mbus.wbusy.eq(1),
mbus.rbusy.eq(1), mbus.rbusy.eq(1),
If(idbus.ack, If(idbus.ack,
mbus.wbusy.eq(0),
mbus.rbusy.eq(0),
latch.eq(1), latch.eq(1),
NextState("IDLE") NextState("WAIT")
)
)
fsm.act("WRITE",
idbus.stb.eq(1),
idbus.cyc.eq(1),
idbus.we.eq(1),
mbus.wbusy.eq(1),
If(idbus.ack,
NextState("IDLE")
) )
) )
# Latch RData on Wishbone ack. # Latch RData on Wishbone ack.
self.sync += If(latch, mbus.rdata.eq(idbus.dat_r)) mbus_rdata = Signal(32)
self.sync += If(latch, mbus_rdata.eq(idbus.dat_r))
self.comb += mbus.rdata.eq(mbus_rdata) # Latched value.
self.comb += If(latch, mbus.rdata.eq(idbus.dat_r)) # Immediate value.
# Main Ram accesses debug.
if False:
self.sync += If(mbus.addr[28:32] == 0x4, # Only Display Main Ram accesses.
If(idbus.stb & idbus.ack,
If(idbus.we,
Display("Write: Addr 0x%08x : Data 0x%08x, Sel: 0x%x", idbus.adr, idbus.dat_w, idbus.sel)
).Else(
Display("Read: Addr 0x%08x : Data 0x%08x", idbus.adr, idbus.dat_r)
)
)
)
# Add Verilog sources. # Add Verilog sources.
# -------------------- # --------------------