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pipistrello: add por reset counter 

* this is a temporary fix that should be removed once the
combination of bitstream-in-flash, mor1kx, bios-in-flash works
This commit is contained in:
Robert Jordens 2015-03-26 14:12:35 -06:00 committed by Sebastien Bourdeauducq
parent 340014dbac
commit 54c14c7119
1 changed files with 6 additions and 1 deletions
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7
targets/pipistrello.py
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@ -58,7 +58,12 @@ class _CRG(Module):
) )
self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk) self.specials += Instance("BUFG", i_I=pll[5], o_O=self.cd_sys.clk)
reset = platform.request("user_btn") reset = platform.request("user_btn")
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | reset) self.clock_domains.cd_por = ClockDomain()
por = Signal(max=1 << 11, reset=(1 << 11) - 1)
self.sync.por += If(por != 0, por.eq(por - 1))
self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
self.specials += AsyncResetSynchronizer(self.cd_por, reset)
self.specials += AsyncResetSynchronizer(self.cd_sys, ~pll_lckd | (por > 0))
self.specials += Instance("BUFG", i_I=pll[2], o_O=self.cd_sdram_half.clk) self.specials += Instance("BUFG", i_I=pll[2], o_O=self.cd_sdram_half.clk)
self.specials += Instance("BUFPLL", p_DIVIDE=4, self.specials += Instance("BUFPLL", p_DIVIDE=4,
i_PLLIN=pll[0], i_GCLK=self.cd_sys.clk, i_PLLIN=pll[0], i_GCLK=self.cd_sys.clk,