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move lm32/mor1kx submodules to extcores

This commit is contained in:
Florent Kermarrec 2015-02-16 10:05:04 +01:00 committed by Sebastien Bourdeauducq
parent 4c9554b65c
commit 5500c41915
7 changed files with 9 additions and 9 deletions
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8
.gitmodules vendored
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@ -1,8 +1,8 @@
[submodule "verilog/lm32/submodule"] [submodule "extcores/lm32/submodule"]
path = verilog/lm32/submodule path = extcores/lm32/submodule
url = https://github.com/m-labs/lm32.git url = https://github.com/m-labs/lm32.git
[submodule "verilog/mor1kx/submodule"] [submodule "extcores/mor1kx/submodule"]
path = verilog/mor1kx/submodule path = extcores/mor1kx/submodule
url = https://github.com/openrisc/mor1kx.git url = https://github.com/openrisc/mor1kx.git
[submodule "software/compiler-rt"] [submodule "software/compiler-rt"]
path = software/compiler-rt path = software/compiler-rt

0
verilog/lm32/lm32_config.v → extcores/lm32/lm32_config.v
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1
extcores/lm32/submodule Submodule

@ -0,0 +1 @@
Subproject commit 84b3e3ca0ad9535acaef201c1482342871358b08

1
extcores/mor1kx/submodule Submodule

@ -0,0 +1 @@
Subproject commit 95fc8e432d762e48b42991663cf9d0cdb918e27e

6
misoclib/gensoc/__init__.py
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@ -75,15 +75,15 @@ class GenSoC(Module):
# add CPU Verilog sources # add CPU Verilog sources
if cpu_type == "lm32": if cpu_type == "lm32":
platform.add_sources(os.path.join("verilog", "lm32", "submodule", "rtl"), platform.add_sources(os.path.join("extcores", "lm32", "submodule", "rtl"),
"lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v", "lm32_cpu.v", "lm32_instruction_unit.v", "lm32_decoder.v",
"lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v", "lm32_load_store_unit.v", "lm32_adder.v", "lm32_addsub.v", "lm32_logic_op.v",
"lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v", "lm32_shifter.v", "lm32_multiplier.v", "lm32_mc_arithmetic.v",
"lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v", "lm32_interrupt.v", "lm32_ram.v", "lm32_dp_ram.v", "lm32_icache.v",
"lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v") "lm32_dcache.v", "lm32_debug.v", "lm32_itlb.v", "lm32_dtlb.v")
platform.add_verilog_include_path(os.path.join("verilog", "lm32")) platform.add_verilog_include_path(os.path.join("extcores", "lm32"))
if cpu_type == "or1k": if cpu_type == "or1k":
platform.add_source_dir(os.path.join("verilog", "mor1kx", "submodule", "rtl", "verilog")) platform.add_source_dir(os.path.join("extcores", "mor1kx", "submodule", "rtl", "verilog"))
def register_rom(self, rom_wb_if, bios_size=0xa000): def register_rom(self, rom_wb_if, bios_size=0xa000):
if self._rom_registered: if self._rom_registered:

1
verilog/lm32/submodule

@ -1 +0,0 @@
Subproject commit dfd6ca7bfc1cf0a6ff306cb95bcae62915091301

1
verilog/mor1kx/submodule

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Subproject commit 64651c8af488a498f059c54fcd9580b1d16ac6c4