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tools/litex_sim: Rename with-bist args to --with-sdram-bist.

This commit is contained in:
Florent Kermarrec 2023-01-20 19:12:42 +01:00
parent 13fcbca4dc
commit 556c8a7755
1 changed files with 4 additions and 4 deletions
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8
litex/tools/litex_sim.py
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@ -138,6 +138,7 @@ class Platform(SimPlatform):
class SimSoC(SoCCore): class SimSoC(SoCCore):
def __init__(self, def __init__(self,
with_sdram = False, with_sdram = False,
with_sdram_bist = False,
with_ethernet = False, with_ethernet = False,
ethernet_phy_model = "sim", ethernet_phy_model = "sim",
with_etherbone = False, with_etherbone = False,
@ -149,7 +150,6 @@ class SimSoC(SoCCore):
sdram_data_width = 32, sdram_data_width = 32,
sdram_spd_data = None, sdram_spd_data = None,
sdram_verbosity = 0, sdram_verbosity = 0,
with_bist = False,
with_i2c = False, with_i2c = False,
with_sdcard = False, with_sdcard = False,
with_spi_flash = False, with_spi_flash = False,
@ -197,7 +197,7 @@ class SimSoC(SoCCore):
l2_cache_size = kwargs.get("l2_size", 8192), l2_cache_size = kwargs.get("l2_size", 8192),
l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128), l2_cache_min_data_width = kwargs.get("min_l2_data_width", 128),
l2_cache_reverse = False, l2_cache_reverse = False,
with_bist = with_bist with_bist = with_sdram_bist
) )
if sdram_init != []: if sdram_init != []:
# Skip SDRAM test to avoid corrupting pre-initialized contents. # Skip SDRAM test to avoid corrupting pre-initialized contents.
@ -370,12 +370,12 @@ def sim_args(parser):
# DRAM. # DRAM.
parser.add_argument("--with-sdram", action="store_true", help="Enable SDRAM support.") parser.add_argument("--with-sdram", action="store_true", help="Enable SDRAM support.")
parser.add_argument("--with-sdram-bist", action="store_true", help="Enable SDRAM BIST Generator/Checker modules.")
parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip.") parser.add_argument("--sdram-module", default="MT48LC16M16", help="Select SDRAM chip.")
parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width.") parser.add_argument("--sdram-data-width", default=32, help="Set SDRAM chip data width.")
parser.add_argument("--sdram-init", default=None, help="SDRAM init file (.bin or .json).") parser.add_argument("--sdram-init", default=None, help="SDRAM init file (.bin or .json).")
parser.add_argument("--sdram-from-spd-dump", default=None, help="Generate SDRAM module based on data from SPD EEPROM dump.") parser.add_argument("--sdram-from-spd-dump", default=None, help="Generate SDRAM module based on data from SPD EEPROM dump.")
parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity.") parser.add_argument("--sdram-verbosity", default=0, help="Set SDRAM checker verbosity.")
parser.add_argument("--with-bist", action="store_true", help="Enable SDRAM BIST modules.")
# Ethernet /Etherbone. # Ethernet /Etherbone.
parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.") parser.add_argument("--with-ethernet", action="store_true", help="Enable Ethernet support.")
@ -479,7 +479,7 @@ def main():
# SoC ------------------------------------------------------------------------------------------ # SoC ------------------------------------------------------------------------------------------
soc = SimSoC( soc = SimSoC(
with_sdram = args.with_sdram, with_sdram = args.with_sdram,
with_bist = args.with_bist, with_sdram_bist = args.with_sdram_bist,
with_ethernet = args.with_ethernet, with_ethernet = args.with_ethernet,
ethernet_phy_model = args.ethernet_phy_model, ethernet_phy_model = args.ethernet_phy_model,
with_etherbone = args.with_etherbone, with_etherbone = args.with_etherbone,