test: fix link_tb and bist_tb

lib/sata/link/__init__.py

@@ -158,7 +158,7 @@ class SATALinkRX(Module):
 		]
 		cont_source_data_d = Signal(32)
 		self.sync += \
-			If(cont.source.stb,
+			If(cont.source.stb & (det == 0),
 				scrambler.sink.d.eq(cont.source.data)
 			)
 
@@ -177,12 +177,12 @@ class SATALinkRX(Module):
 		)
 		fsm.act("WAIT_FIRST",
 			insert.eq(primitives["R_IP"]),
-			If(cont.source.stb,
+			If(cont.source.stb & (det == 0),
 				NextState("COPY")
 			)
 		)
 		fsm.act("COPY",
-			scrambler.sink.stb.eq(cont.source.stb),
+			scrambler.sink.stb.eq(cont.source.stb & ((det == 0) | eop)),
 			scrambler.sink.sop.eq(sop),
 			scrambler.sink.eop.eq(eop),
 			insert.eq(primitives["R_IP"]),

lib/sata/test/bist_tb.py

@@ -1,6 +1,6 @@
 from lib.sata.common import *
 from lib.sata import SATACON
-from lib.sata.bist import SATABIST
+from lib.sata.bist import SATABISTUnit
 
 from lib.sata.test.hdd import *
 from lib.sata.test.common import *
@@ -11,14 +11,8 @@ class TB(Module):
 				link_debug=False, link_random_level=0,
 				transport_debug=False, transport_loopback=False,
 				hdd_debug=True)
-		self.controller = SATACON(self.hdd.phy)
-		self.bist = SATABIST()
-
-		self.pipeline = Pipeline(
-			self.bist,
-			self.controller,
-			self.bist
-		)
+		self.con = SATACON(self.hdd.phy)
+		self.bist = SATABISTUnit(self.con)
 
 	def gen_simulation(self, selfp):
 		hdd = self.hdd

lib/sata/transport/__init__.py

@@ -18,18 +18,6 @@ def _encode_cmd(obj, description, signal):
 		r.append(signal[start:end].eq(item))
 	return r
 
-def _change_endianness(v):
-	r = []
-	for i in range(4):
-		r.append(v[8*(3-i):8*(3-i+1)])
-	return Cat(*r)
-
-def _big2little(v):
-	return _change_endianness(v)
-
-def _little2big(v):
-	return _change_endianness(v)
-
 class SATATransportTX(Module):
 	def __init__(self, link):
 		self.sink = sink = Sink(transport_tx_description(32))