bank: add RE signal for registers made of fields
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parent
92dfbb92dd
commit
55a265d967
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@ -34,6 +34,7 @@ class Bank:
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bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
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bwra.append(field.storage.eq(self.interface.dat_w[offset:offset+field.size]))
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offset += field.size
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offset += field.size
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if len(bwra) > 1:
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if len(bwra) > 1:
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bwra.append(reg.re.eq(1))
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bwcases.append(bwra)
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bwcases.append(bwra)
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else:
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else:
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raise TypeError
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raise TypeError
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@ -27,9 +27,13 @@ class Field:
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self.we = Signal()
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self.we = Signal()
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class RegisterFields:
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class RegisterFields:
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def __init__(self, name, fields):
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def __init__(self, name, fields, re=None):
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self.name = name
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self.name = name
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self.fields = fields
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self.fields = fields
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if re is None:
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self.re = Signal()
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else:
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self.re = re
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class RegisterField(RegisterFields):
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class RegisterField(RegisterFields):
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def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0):
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def __init__(self, name, size=1, access_bus=READ_WRITE, access_dev=READ_ONLY, reset=0):
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@ -71,7 +75,7 @@ def expand_description(description, busword):
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else:
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else:
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f.append(field)
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f.append(field)
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if f:
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if f:
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d.append(RegisterFields(reg.name, f))
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d.append(RegisterFields(reg.name, f, reg.re))
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else:
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else:
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raise TypeError
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raise TypeError
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return d
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return d
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