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adapt to litedram changes

This commit is contained in:
Florent Kermarrec 2016-05-04 00:59:02 +02:00
parent 7a7b9420e6
commit 55c9c653e0
2 changed files with 6 additions and 5 deletions
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3
litex/boards/targets/sim.py
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@ -12,7 +12,8 @@ from litex.soc.integration.builder import *
from litex.soc.cores import uart from litex.soc.cores import uart
from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_core import mem_decoder
from litedram.modules import PhySettings, IS42S16160 from litedram.common import PhySettings
from litedram.modules import IS42S16160
from litedram.phy.model import SDRAMPHYModel from litedram.phy.model import SDRAMPHYModel
from liteeth.phy.model import LiteEthPHYModel from liteeth.phy.model import LiteEthPHYModel

8
litex/soc/integration/soc_sdram.py
View File

@ -14,7 +14,7 @@ __all__ = ["SoCSDRAM", "soc_sdram_args", "soc_sdram_argdict"]
class ControllerInjector(Module, AutoCSR): class ControllerInjector(Module, AutoCSR):
def __init__(self, phy, geom_settings, timing_settings, controller_settings): def __init__(self, phy, geom_settings, timing_settings, **kwargs):
self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits, self.submodules.dfii = dfii.DFIInjector(geom_settings.addressbits, geom_settings.bankbits,
phy.settings.dfi_databits, phy.settings.nphases) phy.settings.dfi_databits, phy.settings.nphases)
self.comb += self.dfii.master.connect(phy.dfi) self.comb += self.dfii.master.connect(phy.dfi)
@ -22,7 +22,7 @@ class ControllerInjector(Module, AutoCSR):
self.submodules.controller = controller = core.LiteDRAMController(phy.settings, self.submodules.controller = controller = core.LiteDRAMController(phy.settings,
geom_settings, geom_settings,
timing_settings, timing_settings,
controller_settings) **kwargs)
self.comb += controller.dfi.connect(self.dfii.slave) self.comb += controller.dfi.connect(self.dfii.slave)
self.submodules.crossbar = crossbar.LiteDRAMCrossbar(controller.interface, controller.nrowbits) self.submodules.crossbar = crossbar.LiteDRAMCrossbar(controller.interface, controller.nrowbits)
@ -48,14 +48,14 @@ class SoCSDRAM(SoCCore):
raise FinalizeError raise FinalizeError
self._wb_sdram_ifs.append(interface) self._wb_sdram_ifs.append(interface)
def register_sdram(self, phy, geom_settings, timing_settings, controller_settings=None): def register_sdram(self, phy, geom_settings, timing_settings, **kwargs):
assert not self._sdram_phy assert not self._sdram_phy
self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning self._sdram_phy.append(phy) # encapsulate in list to prevent CSR scanning
self.submodules.sdram = ControllerInjector(phy, self.submodules.sdram = ControllerInjector(phy,
geom_settings, geom_settings,
timing_settings, timing_settings,
controller_settings) **kwargs)
dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2 dfi_databits_divisor = 1 if phy.settings.memtype == "SDR" else 2
sdram_width = phy.settings.dfi_databits//dfi_databits_divisor sdram_width = phy.settings.dfi_databits//dfi_databits_divisor